omap_mib: Register Map

Generated by tools/regmap.py from hdl/omap_mib/regs/omap_regs.yml, do not edit. The same description generates the VHDL package omap_regs_pkg and the C header sw/omap_regs.h.

Byte addresses of 32-bit registers on the AXI4-Lite port (10-bit address); unused addresses and bits read as zero. The ID register reads 0x4F4D4101.

Access	Meaning
RO	Read only
RW	Read and write
W1	Write one: command; reads as zero
W1C	Sticky flag; write one to clear
WO	Write only; reads as zero
RC	Read only; any write to the register clears it

Registers

Address	Register	Description
0x000	ID	Identification of the core and version of the register map
0x004	GENERICS	Generics of the core
0x008	BUFFERS	Buffer sizes of the Target
0x010	TGT_LA	Logical addresses of the Target (ECSS 5.3.3.5.3)
0x014	TGT_KEY	Key of the Target (ECSS 5.3.3.5.2)
0x018	TGT_LAST	Last command of the Target with an intact header
0x01C	TGT_LAST_TID	Transaction Identifier of the last command
0x020	TGT_LAST_ADDR	Address of the last command
0x024	TGT_LAST_ADDR_EXT	Extended Address of the last command
0x030	TGT_CNT_OK	Commands of the Target executed with status 0
0x034	TGT_CNT_OK2	Read-modify-write commands and replies of the Target
0x038	TGT_CNT_HDR	Packets discarded by the Target without reply (ECSS 5.3.3.4.2, 5.3.3.4.5, 5.7.1.3c)
0x03C	TGT_CNT_ERR1	Commands with the status codes 1 and 2
0x040	TGT_CNT_ERR2	Commands with the status codes 3 and 4
0x044	TGT_CNT_ERR3	Commands with the status codes 5 and 6
0x048	TGT_CNT_ERR4	Commands with the status codes 7 and 9
0x04C	TGT_CNT_ERR5	Commands with the status codes 10 and 11
0x050	TGT_CNT_ERR6	Commands with the status code 12 and replies received by the Target
0x060	INI_TIMEOUT	Reply timeout of the Initiator (ECSS 4.3.1)
0x064	INI_STATUS	Status of the Initiator
0x068	INI_CNT1	Commands sent and replies confirmed by the Initiator
0x06C	INI_CNT2	Corrupted replies at the Initiator (ECSS 5.3.3.11, 5.4.3.11, 5.4.3.12)
0x070	INI_CNT3	Unexpected replies and timeouts
0x074	INI_CNT4	Rejected requests and commands received by an Initiator-only node
0x080	PKT_CNT	Packets of other protocols
0x090	EVENTS	Event flags
0x094	IRQ_EN	Interrupt enable of the event flags
0x098	IRQ_STATUS	Interrupt output
0x0A0	ECC_STATUS	EDAC status of the buffers
0x0A4	ECC_SELECT	Channel shown in ECC_COUNT
0x0A8	ECC_COUNT	SEC and DED counters of the selected channel
0x0AC	ECC_INJECT	Error injection into the next word written to a buffer (tests)
0x100 + 0x10 n	WIN_CTRL	Enable and permissions of window n, high bytes of the 40-bit bounds
0x104 + 0x10 n	WIN_BASE	First address of window n, bits 31 to 0
0x108 + 0x10 n	WIN_LAST	Last address of window n (inclusive), bits 31 to 0

Address windows of the Target (architecture D8), instance n = 0 to Windows_g - 1, for 8 instances.

Fields

ID

Address 0x000: Identification of the core and version of the register map.

Bits	Field	Access	Reset	Description
31:0	ID	RO	0x4F4D4101	0x4F4D41 (OMA) and register map version 1

GENERICS

Address 0x004: Generics of the core.

Bits	Field	Access	Reset	Description
28:24	TGT_ADDR_BYTES	RO	TgtAddrBytes_g	Maximum Target SpaceWire Address of the Initiator in bytes
23:16	WORD_BYTES	RO	AxiDataWidth_g / 8	Bytes of the AXI data word (memory word of single-address accesses)
15:8	TRANSACTIONS	RO	Transactions_g	Entries of the transaction table of the Initiator
7:4	WINDOWS	RO	Windows_g	Number of address windows
3	EXT_AUTH	RO	ExtAuth_g	External authorisation port
2	PASSTHROUGH	RO	Passthrough_g	User port for packets of other protocols
1	INITIATOR	RO	Initiator_g	RMAP Initiator implemented
0	TARGET	RO	Target_g	RMAP Target implemented

BUFFERS

Address 0x008: Buffer sizes of the Target.

Bits	Field	Access	Reset	Description
31:16	CHUNK_BYTES	RO	ChunkBytes_g	Chunk of a non-verified write
15:0	VERIFY_BYTES	RO	BufferBytes_g	Maximum Data Length of a verified write

TGT_LA

Address 0x010: Logical addresses of the Target (ECSS 5.3.3.5.3).

Bits	Field	Access	Reset	Description
18	DEF_LA_EN	RW	DefLaEn_g	Default logical address 0xFE accepted (ECSS 5.1.2 note 2)
17	LA1_EN	RW	0	Second logical address accepted
16	LA0_EN	RW	1	First logical address accepted
15:8	LA1	RW	La1_g	Second logical address
7:0	LA0	RW	La0_g	First logical address

TGT_KEY

Address 0x014: Key of the Target (ECSS 5.3.3.5.2).

Bits	Field	Access	Reset	Description
8	KEY_EN	RW	1	Key checked; '0' accepts every key
7:0	KEY	RW	Key_g	Expected key

TGT_LAST

Address 0x018: Last command of the Target with an intact header.

Bits	Field	Access	Reset	Description
24	REPLIED	RO		Reply sent
23:16	ILA	RO		Initiator Logical Address
15:8	INSTR	RO		Instruction
7:0	STATUS	RO		Status of the command

TGT_LAST_TID

Address 0x01C: Transaction Identifier of the last command.

Bits	Field	Access	Reset	Description
15:0	TID	RO		Transaction Identifier

TGT_LAST_ADDR

Address 0x020: Address of the last command.

Bits	Field	Access	Reset	Description
31:0	ADDR	RO		Address field

TGT_LAST_ADDR_EXT

Address 0x024: Extended Address of the last command.

Bits	Field	Access	Reset	Description
7:0	EXT	RO		Extended Address field

TGT_CNT_OK

Address 0x030: Commands of the Target executed with status 0.

Bits	Field	Access	Reset	Description
31:16	READ	RC	0	Read commands
15:0	WRITE	RC	0	Write commands

TGT_CNT_OK2

Address 0x034: Read-modify-write commands and replies of the Target.

Bits	Field	Access	Reset	Description
31:16	REPLIES	RC	0	Replies sent
15:0	RMW	RC	0	Read-modify-write commands with status 0

TGT_CNT_HDR

Address 0x038: Packets discarded by the Target without reply (ECSS 5.3.3.4.2, 5.3.3.4.5, 5.7.1.3c).

Bits	Field	Access	Reset	Description
31:16	HDR_SHORT	RC	0	End of the packet before the Header CRC
15:0	HDR_CRC	RC	0	Header CRC errors

TGT_CNT_ERR1

Address 0x03C: Commands with the status codes 1 and 2.

Bits	Field	Access	Reset	Description
31:16	UNUSED	RC	0	Unused packet type or command code (2)
15:0	GENERAL	RC	0	General error (1): memory error

TGT_CNT_ERR2

Address 0x040: Commands with the status codes 3 and 4.

Bits	Field	Access	Reset	Description
31:16	DATA_CRC	RC	0	Invalid Data CRC (4)
15:0	KEY	RC	0	Invalid key (3)

TGT_CNT_ERR3

Address 0x044: Commands with the status codes 5 and 6.

Bits	Field	Access	Reset	Description
31:16	TOO_MUCH	RC	0	Too much data (6)
15:0	EARLY_EOP	RC	0	Early EOP (5)

TGT_CNT_ERR4

Address 0x048: Commands with the status codes 7 and 9.

Bits	Field	Access	Reset	Description
31:16	VERIFY_OVERRUN	RC	0	Verify buffer overrun (9)
15:0	EEP	RC	0	EEP (7), including an EEP immediately after the header

TGT_CNT_ERR5

Address 0x04C: Commands with the status codes 10 and 11.

Bits	Field	Access	Reset	Description
31:16	RMW_LENGTH	RC	0	Read-modify-write Data Length error (11)
15:0	NOT_AUTH	RC	0	Command not implemented or not authorised (10)

TGT_CNT_ERR6

Address 0x050: Commands with the status code 12 and replies received by the Target.

Bits	Field	Access	Reset	Description
31:16	REPLY_RX	RC	0	Replies received by the Target (ECSS 5.7.1.3c)
15:0	TLA	RC	0	Invalid Target Logical Address (12)

INI_TIMEOUT

Address 0x060: Reply timeout of the Initiator (ECSS 4.3.1).

Bits	Field	Access	Reset	Description
31:16	TIMEOUT	RW	Timeout_g	Timeout in ticks; 0 disables the timeout
15:0	TICK_CYCLES	RW	TickCycles_g	Tick period minus one in clock cycles

INI_STATUS

Address 0x064: Status of the Initiator.

Bits	Field	Access	Reset	Description
7:0	OPEN	RO		Outstanding commands in the transaction table

INI_CNT1

Address 0x068: Commands sent and replies confirmed by the Initiator.

Bits	Field	Access	Reset	Description
31:16	REP_OK	RC	0	Replies confirmed without error
15:0	CMD_SENT	RC	0	Commands sent

INI_CNT2

Address 0x06C: Corrupted replies at the Initiator (ECSS 5.3.3.11, 5.4.3.11, 5.4.3.12).

Bits	Field	Access	Reset	Description
31:16	DATA_ERR	RC	0	Replies confirmed with a data error
15:0	HDR_ERR	RC	0	Replies discarded for a header error

INI_CNT3

Address 0x070: Unexpected replies and timeouts.

Bits	Field	Access	Reset	Description
31:16	TIMEOUT	RC	0	Commands confirmed with a timeout
15:0	UNEXPECTED	RC	0	Replies without an outstanding command

INI_CNT4

Address 0x074: Rejected requests and commands received by an Initiator-only node.

Bits	Field	Access	Reset	Description
31:16	CMD_RX	RC	0	Commands received without Target (ECSS 5.7.1.2c)
15:0	TID_BUSY	RC	0	Requests rejected for a Transaction Identifier in use

PKT_CNT

Address 0x080: Packets of other protocols.

Bits	Field	Access	Reset	Description
31:16	DISCARDED	RC	0	Packets discarded (no user port)
15:0	USER	RC	0	Packets passed to the user port

EVENTS

Address 0x090: Event flags.

Bits	Field	Access	Reset	Description
8	PKT_DISCARD	W1C	0	Packet discarded by the packet routing
7	ECC_DED	W1C	0	Double error detected in a buffer
6	ECC_SEC	W1C	0	Single error corrected in a buffer
5	INI_TIMEOUT	W1C	0	Command of the Initiator confirmed with a timeout
4	INI_ERROR	W1C	0	Reply of the Initiator discarded, unexpected or with a data error, or request rejected
3	INI_REPLY	W1C	0	Reply confirmed without error
2	TGT_CMD	W1C	0	Command of the Target executed with status 0
1	TGT_DISCARD	W1C	0	Packet discarded by the Target without reply
0	TGT_ERROR	W1C	0	Command of the Target ended with a status other than 0

IRQ_EN

Address 0x094: Interrupt enable of the event flags.

Bits	Field	Access	Reset	Description
8:0	ENABLE	RW	0	Bit n enables EVENTS bit n

IRQ_STATUS

Address 0x098: Interrupt output.

Bits	Field	Access	Reset	Description
0	IRQ	RO		Irq: OR of the enabled event flags

ECC_STATUS

Address 0x0A0: EDAC status of the buffers.

Bits	Field	Access	Reset	Description
2:0	DED	RC	0	Bit n: double error detected in channel n (0 write buffer of the Target, 1 write data of the AXI master, 2 read data of the AXI master); any write clears all counters and flags

ECC_SELECT

Address 0x0A4: Channel shown in ECC_COUNT.

Bits	Field	Access	Reset	Description
1:0	CHANNEL	RW	0	Channel 0 to 2

ECC_COUNT

Address 0x0A8: SEC and DED counters of the selected channel.

Bits	Field	Access	Reset	Description
31:16	DED	RC	0	Double errors detected
15:0	SEC	RC	0	Single errors corrected; any write clears the selected channel

ECC_INJECT

Address 0x0AC: Error injection into the next word written to a buffer (tests).

Bits	Field	Access	Reset	Description
9	DOUBLE	W1	0	Inject a double error
8	SINGLE	W1	0	Inject a single error
1:0	CHANNEL	WO	0	Channel 0 to 2

WIN_CTRL

Address 0x100 + 0x10 n: Enable and permissions of window n, high bytes of the 40-bit bounds.

Bits	Field	Access	Reset	Description
23:16	LAST_EXT	RW	WinInit_g(n)	Bits 39 to 32 of the last address
15:8	BASE_EXT	RW	WinInit_g(n)	Bits 39 to 32 of the first address
5	SINGLE	RW	WinInit_g(n)	Single-address accesses permitted
4	RMW	RW	WinInit_g(n)	Read-modify-write commands permitted
3	VERIFIED_ONLY	RW	WinInit_g(n)	Write commands only with the verify bit set
2	WRITE	RW	WinInit_g(n)	Write commands permitted
1	READ	RW	WinInit_g(n)	Read commands permitted
0	ENABLE	RW	WinInit_g(n)	Window enabled

WIN_BASE

Address 0x104 + 0x10 n: First address of window n, bits 31 to 0.

Bits	Field	Access	Reset	Description
31:0	ADDR	RW	WinInit_g(n)	First address

WIN_LAST

Address 0x108 + 0x10 n: Last address of window n (inclusive), bits 31 to 0.

Bits	Field	Access	Reset	Description
31:0	ADDR	RW	WinInit_g(n)	Last address