crcUpdate(crc, data) returns the CRC after one more byte. ECSS 5.2 forms the polynomial m(x) from the bytes in
transmission order with the least significant bit of each byte first and stores the remainder in reversed bit order
(bit 0 of the CRC byte is the coefficient of x^7). In this bit order the CRC register shifts right: the byte is
added to the register, and eight times the register shifts right by one and adds 0xE0 (the reversed polynomial
without x^8) when the bit shifted out is '1'. The register starts at zero. The RTL decoders and encoders apply the
function once per byte; it unrolls to two levels of XOR.
omapTestEnd, the AXI4-Stream BFM configuration, omapPacket (bytes plus end of packet marker beat)
omap_tb_rmap_pkg.vhd
RMAP model: TbCmd_t with all command fields, tbCommand (command with optional CRC errors), tbWriteReply, tbReadReply, tbReplyPath, CRC with the table of ECSS Annex A.3, byte array helpers
omap_tb_mem_pkg.vhd, omap_tb_memvar_pkg.vhd
Memory of the AXI memory model as a protected type with one instance per model: backdoor access, error ranges, backpressure, statistics
omap_tb_axi_ram.vhd
AXI memory model: AXI4 slave with INCR bursts, write strobes, 16 queued commands per direction, SLVERR on the error ranges (bytes in a write error range are not written), random backpressure