| CORE-IF-01 |
The core shall offer the AXI4-Stream ports of ofb_ni, the AXI4-Lite port and interrupt of ofb_mib, and per lane the symbol stream and control of the Physical adapter as defined by ofb_lane. |
6.2, 6.3, 6.5, 5.5.1k to n |
| CORE-CK-01 |
The core shall run on four clocks: UserClk, CoreClk, LaneClk and MgmtClk; CoreClk shall not be slower than LaneClk. |
none (architecture section 6) |
| CORE-RS-01 |
One asynchronous reset input shall reset every clock domain through a reset generator per domain. |
5.7.9.2a.1 (power-on reset) |
| CORE-CC-02 |
A receive row lost because the crossing FIFO is full (CoreClk slower than LaneClk, outside CORE-CK-01) shall be reported to the MIB. |
5.9.4c |
| CORE-CC-01 |
Rows shall cross between CoreClk and LaneClk through FIFOs that are flushed on link reset; link reset and LaneReset shall cross as pulses, the near-end capability as a level, the far-end capability event together with its "no lane active" qualifier. |
5.7.9, 5.7.10b |
| CORE-SY-01 |
Two cores connected through their Physical adapters shall initialise the link when started through the MIB, transfer packets and broadcast messages without loss, recover from bit errors and reset both ends on a Link Reset command. |
5.5 to 5.9 (system level) |
| CORE-ML-01 |
With several lanes, all Lane layers shall send SKIP on the SKIP request of the Multi-Lane layer; the Multi-Lane management parameters (TxEn, RxEn, maximum number of data-sending lanes, bypass) shall reach the Multi-Lane layer and the Data Link layer from the MIB, and the Multi-Lane status (data-sending and data-receiving lanes, alignment state, bypass, Misaligned events) the MIB. |
5.6.1p, q, 5.6.4.5a, Tables 5-36, 5-37 |
| CORE-ED-01 |
The SEC and DED events of all fault-tolerant buffers shall reach the EDAC monitor of the MIB, and errors shall be injectable into every channel through the MIB. |
none (fault tolerance, MG-3) |
| CORE-ED-02 |
An uncorrectable error (DED) in a row crossing shall not corrupt data silently: a received row with a DED shall be passed to the Data Link layer as one RXERR, a transmitted row with a DED shall be sent as a full row of poisoned words (ML-DS-13), so that the far end discards the frame and requests its retransmission. |
none (fault tolerance, P5); 5.7.7.2.2 |
| CORE-FT-01 |
Two cores shall deliver every packet and broadcast message unchanged and in order, without link reset, while random single faults occur during traffic: bit errors and bursts of bit errors (up to 8 symbols) on the lines, word slips, single errors in any fault-tolerant buffer, double errors in the row crossings and, with 2 or 4 lanes, the failure and reconnection of a lane; the EDAC monitor shall report the buffer errors. |
5.7.7.1, 5.7.7.2.3, 5.7.7.3, 5.6.6.1 (system level) |
| CORE-PL-01 |
The serial loopback enables of the MIB shall be outputs per lane for the Physical adapter (Phy_SerialNearLoopback, Phy_SerialFarLoopback, LaneClk). |
5.4.1h, 5.4.2.2 |
| CORE-PL-02 |
The bit synchronisation status of the Physical adapter per lane (Phy_BitSync, LaneClk, not synchronised when left open) shall be passed to the MIB. |
5.4.2e |
| CORE-PL-03 |
The PRBS test of the MIB (MG-5) shall connect to the Physical adapters per lane (LaneClk): transmitted and checked pattern (Phy_PrbsTxSel, Phy_PrbsRxSel), force error and checker reset pulses (Phy_PrbsForceErr, Phy_PrbsCntReset), checker error and lock (Phy_PrbsErr, Phy_PrbsLocked, not locked and without errors when left open). |
none (test function) |
| CORE-PF-01 |
With packets of up to 1024 bytes on all VCs, two cores shall transfer at least 90 % of the payload capacity of the lanes (32 bits per LaneClk cycle and lane) in one direction and at least 85 % in each direction when both ends send. |
none (performance) |
| CORE-SY-02 |
Two cores with 2 or 4 lanes shall transfer packets without loss also when a lane fails and is reconnected during traffic, with fewer data-sending lanes than lanes, and in the Multi-Lane bypass. |
5.6, 5.7.7 (system level) |