ofb_mib: Register Map¶

Generated by tools/regmap.py from hdl/ofb_mib/regs/ofb_regs.yml, do not edit. The same description generates the VHDL package ofb_regs_pkg and the C header sw/ofb_regs.h.

Byte addresses of 32-bit registers on the AXI4-Lite port (12-bit address); unused addresses and bits read as zero. The ID register reads 0x0FB10006.

Access	Meaning
RO	Read only
RW	Read and write
W1	Write one: command; reads as zero
W1C	Sticky flag; write one to clear
WO	Write only; reads as zero
RC	Read only; any write to the register clears it

Registers¶

Address	Register	Description
0x000	ID	Identification of the core and version of the register map
0x004	GENERICS	Generics of the core
0x008	DL_CTRL	Data Link control
0x00C	DL_BC_INTERVAL	Broadcast flow control
0x010	DL_STATUS	Data Link status
0x014	DL_ERRORS	Sticky error flags of the Data Link layer
0x018	DL_RETRIES	Error recovery attempts
0x01C	DL_CRC16_COUNT	CRC-16 errors
0x020	DL_CRC8_COUNT	CRC-8 errors
0x024	DL_FRAME_COUNT	Frame errors
0x028	DL_SEQ_COUNT	Sequence errors
0x030	VC_HAS_CREDIT	Has Credit per VC
0x034	VC_INPUT_OVERFLOW	Input buffer overflow per VC
0x038	VC_CREDIT_OVERFLOW	FCT credit counter overflow per VC
0x03C	VC_FRAMING_ERROR	Framing error of the Network interface per VC
0x040	ML_STATUS	Multi-Lane status
0x044	IRQ_MASK	Interrupt enables
0x048	VC_BW_OVER	Bandwidth over use per VC
0x04C	VC_BW_UNDER	Bandwidth under use per VC
0x050	VC_IDLE_LIMIT	Virtual Channel Idle Time Limit
0x054	SCHED_STATUS	Schedule status
0x058	ML_CTRL	Multi-Lane control
0x05C	ML_MISALIGNED	Misaligned conditions
0x060	ECC_STATUS	EDAC monitor status; any write clears the flags and the counters of all channels
0x064	ECC_SELECT	EDAC channel of ECC_COUNT
0x068	ECC_COUNT	EDAC counters of the channel in ECC_SELECT; any write clears them
0x06C	ECC_INJECT	Error injection into the next word written into the buffers of a channel
0x100 + 0x20 i	LANE_CTRL	Lane control
0x104 + 0x20 i	LANE_STATUS	Lane status
0x108 + 0x20 i	LANE_EVENTS	Sticky lane events
0x10C + 0x20 i	LANE_REASONS	Reasons received from the far end
0x110 + 0x20 i	LANE_TIMEOUT_COUNT	Initialisation timeouts
0x114 + 0x20 i	LANE_PRBS_CTRL	PRBS test of the Physical adapter (bit error rate, 8B/10B bypassed, lane without traffic)
0x118 + 0x20 i	LANE_PRBS_ERRORS	PRBS checker errors
0x11C + 0x20 i	LANE_PRBS_WORDS	PRBS checked words
0x400 + 0x10 v	VC_CFG	VC configuration
0x404 + 0x10 v	VC_BANDWIDTH	Expected bandwidth
0x408 + 0x10 v	VC_SLOTS_LO	Time-slots 31 to 0
0x40C + 0x10 v	VC_SLOTS_HI	Time-slots 63 to 32

Registers of lane i at address + i x 0x20, for NumLanes_g instances.

Quality of service registers of VC v at address + v x 0x10, for NumVc_g instances.

Fields¶

ID¶

Address 0x000: Identification of the core and version of the register map.

Bits	Field	Access	Reset	Description
31:0	ID	RO	0xFB10006	0x0FB1 (OpenFibre) and register map version 6

GENERICS¶

Address 0x004: Generics of the core.

Bits	Field	Access	Reset	Description
11:8	NUM_LANES	RO	NumLanes_g	Number of lanes
7:0	NUM_VC	RO	NumVc_g	Number of virtual channels

DL_CTRL¶

Address 0x008: Data Link control.

Bits	Field	Access	Reset	Description
8	DATA_SCRAMBLED	RW	1	Data scrambling requested from the far end (near-end capability)
1	INTERFACE_RESET	W1	0	Interface Reset command; all configuration registers take their reset values
0	LINK_RESET	W1	0	Link Reset command; also clears the status of the Data Link, Multi-Lane and Lane layers (the EDAC status is kept)

DL_BC_INTERVAL¶

Address 0x00C: Broadcast flow control.

Bits	Field	Access	Reset	Description
15:0	INTERVAL	RW	0x28	Words per broadcast credit (4 / Normalised Expected Broadcast Bandwidth)

DL_STATUS¶

Address 0x010: Data Link status.

Bits	Field	Access	Description
8	ERB_EMPTY	RO	Error recovery buffer empty
6:4	WORD_ID_STATE	RO	Data word identification state machine
3:2	RX_ERR_STATE	RO	Receive error state machine: 0 Valid Positive, 1 Valid Negative, 2 Error Positive, 3 Error Negative
1:0	LINK_STATE	RO	Link reset state machine: 0 Configuration Reset, 1 Near-End Reset, 2 Check Far-End Reset, 3 Link Initialised

DL_ERRORS¶

Address 0x014: Sticky error flags of the Data Link layer.

Bits	Field	Access	Description
10	RX_ROW_OVERFLOW	W1C	Receive row lost in the crossing to the core clock
9	FRAMING_ERROR	W1C	Framing error of the Network interface (any VC)
8	CREDIT_OVERFLOW	W1C	FCT credit overflow (any VC)
7	INPUT_OVERFLOW	W1C	Input buffer overflow (any VC)
6	BC_DISCARD	W1C	Broadcast message discarded
5	FAR_END_LINK_RESET	W1C	Far-End Link Reset
4	PROTOCOL	W1C	Link Reset Caused by Protocol Error
3	SEQUENCE	W1C	Sequence error
2	FRAME	W1C	Frame error
1	CRC8	W1C	CRC-8 error
0	CRC16	W1C	CRC-16 error

DL_RETRIES¶

Address 0x018: Error recovery attempts.

Bits	Field	Access	Reset	Description
31:0	COUNT	RC	0	Number of error recovery attempts

DL_CRC16_COUNT¶

Address 0x01C: CRC-16 errors.

Bits	Field	Access	Reset	Description
15:0	COUNT	RC	0	CRC-16 errors (saturating)

DL_CRC8_COUNT¶

Address 0x020: CRC-8 errors.

Bits	Field	Access	Reset	Description
15:0	COUNT	RC	0	CRC-8 errors (saturating)

DL_FRAME_COUNT¶

Address 0x024: Frame errors.

Bits	Field	Access	Reset	Description
15:0	COUNT	RC	0	Frame errors (saturating)

DL_SEQ_COUNT¶

Address 0x028: Sequence errors.

Bits	Field	Access	Reset	Description
15:0	COUNT	RC	0	Sequence errors (saturating)

VC_HAS_CREDIT¶

Address 0x030: Has Credit per VC.

Bits	Field	Access	Reset	Description
NumVc-1:0	VC	RO		Has Credit of VC v in bit v

VC_INPUT_OVERFLOW¶

Address 0x034: Input buffer overflow per VC.

Bits	Field	Access	Reset	Description
NumVc-1:0	VC	W1C	0	Input buffer overflow of VC v in bit v

VC_CREDIT_OVERFLOW¶

Address 0x038: FCT credit counter overflow per VC.

Bits	Field	Access	Reset	Description
NumVc-1:0	VC	W1C	0	FCT credit counter overflow of VC v in bit v

VC_FRAMING_ERROR¶

Address 0x03C: Framing error of the Network interface per VC.

Bits	Field	Access	Reset	Description
NumVc-1:0	VC	W1C	0	Framing error of VC v in bit v

ML_STATUS¶

Address 0x040: Multi-Lane status.

Bits	Field	Access	Description
10	BYPASS	RO	Multi-Lane bypass active
9:8	ALIGN_STATE	RO	Alignment state machine: 0 Not Ready, 1 Near-End Ready, 2 Both-Ends Ready
7:4	DATA_RECEIVING	RO	Data-receiving lanes
3:0	DATA_SENDING	RO	Data-sending lanes

IRQ_MASK¶

Address 0x044: Interrupt enables.

Bits	Field	Access	Description
25	ECC_SEC	RW	Interrupt enable of the ECC SEC flag
24	ECC_DED	RW	Interrupt enable of the ECC DED flags
19:16	LANE_EVENTS	RW	Interrupt enable of the LANE_EVENTS bits of any lane
10:0	DL_ERRORS	RW	Interrupt enable of the DL_ERRORS bits

VC_BW_OVER¶

Address 0x048: Bandwidth over use per VC.

Bits	Field	Access	Reset	Description
NumVc-1:0	VC	W1C	0	Bandwidth over use of VC v in bit v

VC_BW_UNDER¶

Address 0x04C: Bandwidth under use per VC.

Bits	Field	Access	Reset	Description
NumVc-1:0	VC	W1C	0	Bandwidth under use of VC v in bit v

VC_IDLE_LIMIT¶

Address 0x050: Virtual Channel Idle Time Limit.

Bits	Field	Access	Reset	Description
31:0	LIMIT	RW	0x2625A	Idle time limit in words (1 ms at 6.25 Gbit/s)

SCHED_STATUS¶

Address 0x054: Schedule status.

Bits	Field	Access	Reset	Description
5:0	TIME_SLOT	RO		Current time-slot

ML_CTRL¶

Address 0x058: Multi-Lane control.

Bits	Field	Access	Reset	Description
8	BYPASS	RW	0	Multi-Lane bypass
2:0	MAX_DATA_LANES	RW	NumLanes_g	Maximum number of data-sending lanes (taken over at link reset)

ML_MISALIGNED¶

Address 0x05C: Misaligned conditions.

Bits	Field	Access	Reset	Description
15:0	COUNT	RC	0	Misaligned conditions in Near-End Ready or Both-Ends Ready (saturating)

ECC_STATUS¶

Address 0x060: EDAC monitor status; any write clears the flags and the counters of all channels.

Bits	Field	Access	Reset	Description
16	SEC	RC	0	Corrected error (SEC) seen in any channel
8:0	DED	RC	0	Uncorrectable error (DED) flag per EDAC channel

ECC_SELECT¶

Address 0x064: EDAC channel of ECC_COUNT.

Bits	Field	Access	Reset	Description
3:0	CHANNEL	RW	0	EDAC channel

ECC_COUNT¶

Address 0x068: EDAC counters of the channel in ECC_SELECT; any write clears them.

Bits	Field	Access	Reset	Description
31:16	DED_COUNT	RC	0	Uncorrectable errors (saturating)
15:0	SEC_COUNT	RC	0	Corrected errors (saturating)

ECC_INJECT¶

Address 0x06C: Error injection into the next word written into the buffers of a channel.

Bits	Field	Access	Reset	Description
8	DOUBLE	WO	0	Double error (uncorrectable) instead of a single error
3:0	CHANNEL	WO	0	EDAC channel

LANE_CTRL¶

Address 0x100 + 0x20 i: Lane control.

Bits	Field	Access	Reset	Description
17	SERIAL_FAR_LOOPBACK	RW	0	Far-end serial loopback (Physical layer)
16	SERIAL_NEAR_LOOPBACK	RW	0	Near-end serial loopback (Physical layer)
15:8	STANDBY_REASON	RW	0	Standby Reason sent in STANDBY words
6	RX_EN	RW	1	Receive enable of the Multi-Lane layer (RxEn)
5	TX_EN	RW	1	Transmit enable of the Multi-Lane layer (TxEn)
4	FAR_LOOPBACK	RW	0	Far-end parallel loopback
3	NEAR_LOOPBACK	RW	0	Near-end parallel loopback
2	LANE_RESET	RW	0	LaneReset
1	AUTO_START	RW	1	AutoStart
0	LANE_START	RW	0	LaneStart

LANE_STATUS¶

Address 0x104 + 0x20 i: Lane status.

Bits	Field	Access	Description
23:16	FAR_CAPABILITY	RO	Far-end capabilities
15:8	RXERR_COUNT	RO	RXERR word counter
7	PRBS_LOCKED	RO	PRBS checker of the Physical adapter locked to the received pattern
6	BIT_SYNC	RO	Bit synchronisation of the Physical adapter
5	NO_SIGNAL	RO	No signal at the receiver
4	RX_POLARITY	RO	Receive polarity inverted
3:0	STATE	RO	Lane initialisation state

LANE_EVENTS¶

Address 0x108 + 0x20 i: Sticky lane events.

Bits	Field	Access	Description
3	FAR_LOST_SIGNAL	W1C	Far end lost the signal
2	FAR_STANDBY	W1C	Far end in standby
1	TIMEOUT	W1C	Initialisation timeout
0	RXERR_OVERFLOW	W1C	RXERR counter overflow

LANE_REASONS¶

Address 0x10C + 0x20 i: Reasons received from the far end.

Bits	Field	Access	Reset	Description
15:8	LOST_SIGNAL_REASON	RO		Far-end LOST_SIGNAL reason
7:0	STANDBY_REASON	RO		Far-end Standby Reason

LANE_TIMEOUT_COUNT¶

Address 0x110 + 0x20 i: Initialisation timeouts.

Bits	Field	Access	Reset	Description
15:0	COUNT	RC	0	Initialisation timeouts (saturating)

LANE_PRBS_CTRL¶

Address 0x114 + 0x20 i: PRBS test of the Physical adapter (bit error rate, 8B/10B bypassed, lane without traffic).

Bits	Field	Access	Description
17	FORCE_ERROR	W1	Inserts one bit error into the transmitted pattern
16	COUNT_RESET	W1	Clears the PRBS counters and restarts the lock detection of the checker
8	HOLD	RW	Counters stopped (consistent read of LANE_PRBS_ERRORS and LANE_PRBS_WORDS)
7:4	RX_PATTERN	RW	Checked pattern: 0 checker off, 1 PRBS-7, 2 PRBS-9, 3 PRBS-15, 4 PRBS-23, 5 PRBS-31
3:0	TX_PATTERN	RW	Transmitted pattern: 0 normal data, 1 PRBS-7, 2 PRBS-9, 3 PRBS-15, 4 PRBS-23, 5 PRBS-31 (other values: transceiver test patterns)

LANE_PRBS_ERRORS¶

Address 0x118 + 0x20 i: PRBS checker errors.

Bits	Field	Access	Reset	Description
31:0	COUNT	RO	0	Received words with at least one bit error while the checker is on (saturating)

LANE_PRBS_WORDS¶

Address 0x11C + 0x20 i: PRBS checked words.

Bits	Field	Access	Reset	Description
31:0	COUNT	RO	0	Words checked while the checker is on, in units of 65536 words of 40 bits (saturating)

VC_CFG¶

Address 0x400 + 0x10 v: VC configuration.

Bits	Field	Access	Reset	Description
21:16	VN	RW	v	Virtual network number (VC 0: always 0)
8	CONTINUOUS	RW	0	Continuous mode
3:0	PRIORITY	RW	NumPrio_g-1	Priority level (0 highest)

VC_BANDWIDTH¶

Address 0x404 + 0x10 v: Expected bandwidth.

Bits	Field	Access	Reset	Description
15:0	FACTOR	RW	0x0A00 (VC 0), 0xFFFF	1 / Normalised Expected Bandwidth, 8.8 fixed point (0x0100: 100 %, 0x0A00: 10 %, 0: no bandwidth)

VC_SLOTS_LO¶

Address 0x408 + 0x10 v: Time-slots 31 to 0.

Bits	Field	Access	Reset	Description
31:0	SLOTS	RW	0xFFFFFFFF	Allocated time-slots 31 to 0

VC_SLOTS_HI¶

Address 0x40C + 0x10 v: Time-slots 63 to 32.

Bits	Field	Access	Reset	Description
31:0	SLOTS	RW	0xFFFFFFFF	Allocated time-slots 63 to 32