owr_mib: Register Map

Generated by tools/regmap.py from hdl/owr_mib/regs/owr_regs.yml, do not edit. The same description generates the VHDL package owr_regs_pkg and the C header sw/owr_regs.h.

Byte addresses of 32-bit registers on the AXI4-Lite port (8-bit address); unused addresses and bits read as zero. The ID register reads 0x4F575201.

Access	Meaning
RO	Read only
RW	Read and write
W1	Write one: command; reads as zero
W1C	Sticky flag; write one to clear
WO	Write only; reads as zero
RC	Read only; any write to the register clears it

Registers

Address	Register	Description
0x00	ID	Identification of the core and version of the register map
0x04	GENERICS	Generics of the core
0x08	FIFO_DEPTHS	Depths of the transmit and receive FIFOs in N-Chars
0x0C	CLK_FREQ	Frequency of LinkClk
0x10	PORT_CTRL	Port control: Data Link layer (ECSS 5.5.3a), Physical layer (ECSS 5.3.8) and port loopback (ECSS 5.6.10f)
0x14	LINK_SPEED	Data signalling rate of the transmitter (ECSS 5.4.11): bit period in LinkClk cycles
0x18	PORT_STATUS	Port status (ECSS 5.5.3b)
0x1C	CREDIT	Credit counters (ECSS 5.5.3b.3)
0x20	FIFO_LEVELS	Fill levels of the FIFOs seen from LinkClk
0x24	ERRORS	Error flags (ECSS 5.5.3b.2)
0x28	ERROR_COUNTS	Error counters (saturating)
0x2C	LINK_COUNTS	Link counters (saturating)
0x30	EVENTS	Event flags
0x34	ERRORS_IRQ_EN	Interrupt enable of the error flags
0x38	EVENTS_IRQ_EN	Interrupt enable of the event flags
0x3C	IRQ_STATUS	Interrupt output
0x40	TIME_CODE	Time-code register (ECSS 5.6.4.3)
0x44	TC_SEND	TIME-CODE.request (ECSS 6.1.2.2)
0x48	TC_COUNTS	Time-code counters (saturating)
0x50	INT_CTRL	Distributed interrupt mode (ECSS 5.6.5.1d)
0x54	INT_TICK	Tick of the interrupt timers
0x58	INT_HOLDOFF	Minimum interval between two interrupt codes of one identifier (ECSS 5.6.5.4c, d)
0x5C	INT_ACK_DELAY	Minimum delay between a received interrupt code and its acknowledgement code (ECSS 5.6.5.6e)
0x60	INT_ACTIVE	Interrupt register: interrupts received and not acknowledged
0x64	INT_SEND	DISTRIBUTED_INTERRUPT.request (ECSS 6.1.3.2)
0x68	INT_ACK	DISTRIBUTED_INTERRUPT_ACK.request (ECSS 6.1.3.4)
0x6C	ACK_RECEIVED	Interrupt acknowledgement codes received
0x80	ECC_STATUS	EDAC status of the FIFOs
0x84	ECC_SELECT	Channel shown in ECC_COUNT
0x88	ECC_COUNT	SEC and DED counters of the selected channel
0x8C	ECC_INJECT	Error injection into the next word written to a FIFO (tests)

Fields

ID

Address 0x00: Identification of the core and version of the register map.

Bits	Field	Access	Reset	Description
31:0	ID	RO	0x4F575201	0x4F5752 (OWR) and register map version 1

GENERICS

Address 0x04: Generics of the core.

Bits	Field	Access	Reset	Description
12:8	INT_TIMER_WIDTH	RO	IntTimerWidth_g	Width of the interrupt timers in ticks
1	INTERRUPTS	RO	Interrupts_g	Distributed interrupt service implemented
0	TIME_CODES	RO	TimeCodes_g	Time-code service implemented

FIFO_DEPTHS

Address 0x08: Depths of the transmit and receive FIFOs in N-Chars.

Bits	Field	Access	Reset	Description
31:16	RX	RO	RxFifoDepth_g	Receive FIFO depth
15:0	TX	RO	TxFifoDepth_g	Transmit FIFO depth

CLK_FREQ

Address 0x0C: Frequency of LinkClk.

Bits	Field	Access	Reset	Description
31:0	KHZ	RO	LinkClkFreq_g	Frequency of LinkClk in kHz

PORT_CTRL

Address 0x10: Port control: Data Link layer (ECSS 5.5.3a), Physical layer (ECSS 5.3.8) and port loopback (ECSS 5.6.10f).

Bits	Field	Access	Reset	Description
6	LOOPBACK	RW	0	Port loopback: the receiver receives the own transmitter
5	RECEIVER_EN	RW	1	Enable line receiver
4	DRIVER_EN	RW	1	Enable line driver
3	AUTO_START	RW	AutoStart_g	AutoStart
2	LINK_START	RW	LinkStart_g	LinkStart
1	LINK_DISABLED	RW	LinkDisabled_g	LinkDisabled
0	PORT_RESET	W1	0	PortReset: clears both FIFOs, moves the link state machine to ErrorReset, sets the time-code register to zero and clears the interrupt registers

LINK_SPEED

Address 0x14: Data signalling rate of the transmitter (ECSS 5.4.11): bit period in LinkClk cycles.

Bits	Field	Access	Reset	Description
15:8	INIT_DIV	RO	InitDiv	Bit period outside Run (10 Mb/s)
7:0	RUN_DIV	RW	RunDiv_g	Bit period in the Run state (1 to 255, 0 is treated as 1)

PORT_STATUS

Address 0x18: Port status (ECSS 5.5.3b).

Bits	Field	Access	Reset	Description
10:8	LAST_CAUSE	RO		Cause of the last error recovery (ECSS 5.5.8.4a.5): 0 none, 1 LinkDisabled, 2 disconnect, 3 parity error, 4 ESC error, 5 credit error
5	SPILL	RO		Remainder of a packet being discarded from the transmit FIFO
4	GOT_NULL	RO		gotNull
3	RECOVERY	RO		Link error recovery state machine in Recovery
2:0	LINK_STATE	RO		Link state: 0 ErrorReset, 1 ErrorWait, 2 Ready, 3 Started, 4 Connecting, 5 Run

CREDIT

Address 0x1C: Credit counters (ECSS 5.5.3b.3).

Bits	Field	Access	Reset	Description
13:8	RX_CREDIT	RO		Receive credit count
5:0	TX_CREDIT	RO		Transmit credit count

FIFO_LEVELS

Address 0x20: Fill levels of the FIFOs seen from LinkClk.

Bits	Field	Access	Reset	Description
31:16	RX	RO		Receive FIFO level
15:0	TX	RO		Transmit FIFO level

ERRORS

Address 0x24: Error flags (ECSS 5.5.3b.2).

Bits	Field	Access	Reset	Description
3	CREDIT	W1C	0	Credit error
2	ESC	W1C	0	ESC error
1	PARITY	W1C	0	Parity error
0	DISCONNECT	W1C	0	Disconnect

ERROR_COUNTS

Address 0x28: Error counters (saturating).

Bits	Field	Access	Reset	Description
31:24	CREDIT	RC	0	Credit errors
23:16	ESC	RC	0	ESC errors
15:8	PARITY	RC	0	Parity errors
7:0	DISCONNECT	RC	0	Disconnects

LINK_COUNTS

Address 0x2C: Link counters (saturating).

Bits	Field	Access	Reset	Description
31:16	RECOVERY	RC	0	Link error recoveries
15:0	RUN	RC	0	Entries into the Run state

EVENTS

Address 0x30: Event flags.

Bits	Field	Access	Reset	Description
13	ECC_DED	W1C	0	Double error detected in a FIFO
12	ECC_SEC	W1C	0	Single error corrected in a FIFO
11	RX_OVERFLOW	W1C	0	N-Char lost in the receive handler
10	IND_OVERFLOW	W1C	0	Indication lost (indication FIFO full)
9	ACK_REQ_DISCARDED	W1C	0	Acknowledgement request in interrupt mode (no code sent)
8	INT_REQ_DISCARDED	W1C	0	Interrupt request within the minimum interval or while waiting
7	BC_IGNORED	W1C	0	Received broadcast code ignored: type 0b01 or 0b11 (ECSS 5.6.3f), disabled service, or acknowledgement in interrupt mode
6	BC_DISCARDED	W1C	0	Broadcast code discarded by the Data Link layer outside Run (ECSS 5.5.9)
5	ACK_RECEIVED	W1C	0	Interrupt acknowledgement code received
4	INT_RECEIVED	W1C	0	Interrupt code received
3	TC_INVALID	W1C	0	Invalid time-code received
2	TC_VALID	W1C	0	Valid time-code received
1	LINK_DOWN	W1C	0	Run state left
0	LINK_UP	W1C	0	Run state entered

ERRORS_IRQ_EN

Address 0x34: Interrupt enable of the error flags.

Bits	Field	Access	Reset	Description
3:0	ENABLE	RW	0	Bit n enables ERRORS bit n

EVENTS_IRQ_EN

Address 0x38: Interrupt enable of the event flags.

Bits	Field	Access	Reset	Description
13:0	ENABLE	RW	0	Bit n enables EVENTS bit n

IRQ_STATUS

Address 0x3C: Interrupt output.

Bits	Field	Access	Reset	Description
0	IRQ	RO		Irq: OR of the enabled error and event flags

TIME_CODE

Address 0x40: Time-code register (ECSS 5.6.4.3).

Bits	Field	Access	Reset	Description
5:0	VALUE	RO		Last time-code sent or received

TC_SEND

Address 0x44: TIME-CODE.request (ECSS 6.1.2.2).

Bits	Field	Access	Reset	Description
5:0	VALUE	WO	0	A write sends a time-code with this value

TC_COUNTS

Address 0x48: Time-code counters (saturating).

Bits	Field	Access	Reset	Description
31:16	INVALID	RC	0	Invalid time-codes received
15:0	VALID	RC	0	Valid time-codes received

INT_CTRL

Address 0x50: Distributed interrupt mode (ECSS 5.6.5.1d).

Bits	Field	Access	Reset	Description
0	ACK_MODE	RW	0	1: interrupt with acknowledgement mode, 0: interrupt mode

INT_TICK

Address 0x54: Tick of the interrupt timers.

Bits	Field	Access	Reset	Description
15:0	CYCLES	RW	IntTick	Tick period in LinkClk cycles (reset: 1 us; 0 is treated as 1)

INT_HOLDOFF

Address 0x58: Minimum interval between two interrupt codes of one identifier (ECSS 5.6.5.4c, d).

Bits	Field	Access	Reset	Description
IntTimerWidth-1:0	TICKS	RW	0	Interval in ticks; 0: none

INT_ACK_DELAY

Address 0x5C: Minimum delay between a received interrupt code and its acknowledgement code (ECSS 5.6.5.6e).

Bits	Field	Access	Reset	Description
IntTimerWidth-1:0	TICKS	RW	0	Delay in ticks; 0: none

INT_ACTIVE

Address 0x60: Interrupt register: interrupts received and not acknowledged.

Bits	Field	Access	Reset	Description
31:0	IID	RO		Bit n is set by a received interrupt code n and cleared by an acknowledgement request n

INT_SEND

Address 0x64: DISTRIBUTED_INTERRUPT.request (ECSS 6.1.3.2).

Bits	Field	Access	Reset	Description
4:0	IID	WO	0	A write sends an interrupt code with this identifier

INT_ACK

Address 0x68: DISTRIBUTED_INTERRUPT_ACK.request (ECSS 6.1.3.4).

Bits	Field	Access	Reset	Description
4:0	IID	WO	0	A write acknowledges the interrupt with this identifier

ACK_RECEIVED

Address 0x6C: Interrupt acknowledgement codes received.

Bits	Field	Access	Reset	Description
31:0	IID	W1C	0	Bit n is set by a received acknowledgement code n

ECC_STATUS

Address 0x80: EDAC status of the FIFOs.

Bits	Field	Access	Reset	Description
5:0	DED	RC	0	Bit n: double error detected in channel n (0 transmit FIFO, 1 receive FIFO, 2 broadcast requests, 3 broadcast indications, 4 register requests, 5 register responses); any write clears all counters and flags

ECC_SELECT

Address 0x84: Channel shown in ECC_COUNT.

Bits	Field	Access	Reset	Description
2:0	CHANNEL	RW	0	Channel 0 to 5

ECC_COUNT

Address 0x88: SEC and DED counters of the selected channel.

Bits	Field	Access	Reset	Description
31:16	DED	RC	0	Double errors detected
15:0	SEC	RC	0	Single errors corrected; any write clears the selected channel

ECC_INJECT

Address 0x8C: Error injection into the next word written to a FIFO (tests).

Bits	Field	Access	Reset	Description
9	DOUBLE	W1	0	Inject a double error
8	SINGLE	W1	0	Inject a single error
2:0	CHANNEL	WO	0	Channel 0 to 5