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Changelog

4.6.0

04-Jul-2026

Added Features

  • Added olo_fix_mix_r2c
    • Real to complex mixer (fixed-point)
    • Contributed by: obruendl
  • Added olo_fix_mix_c2r
    • Complex to real mixer (fixed-point)
    • Contributed by: obruendl
  • Added olo_fix_coef_storage
    • Fixed-point coefficient memory (RAM or ROM)
    • Contributed by: obruendl
  • Added olo_fix_fir_dec_ser_chtdm
    • FIR decimator with TDM channel handling and serial tap computation (fixed-point)
    • Works with one multiplier, shared between all taps and channels
    • Contributed by: obruendl
  • Added olo_fix_fir_dec_par_chtdm
    • FIR decimator with parallel channel handling and serial tap computation (fixed-point)
    • Works with one multiplier per channel
    • Contributed by: obruendl
  • Added olo_fix_mov_avg
    • Moving average filter (fixed-point)
    • Contributed by: obruendl
  • Added RdEna/RdValid ports to all RAMs
    • This allows for more efficient handling of RAMs with multiple cycles of read latency
    • Contributed by: obruendl
  • In olo_intf_spi_master allow multiple transactions without CSn going high in between

Backward Compatible Changes

  • Speedup questa/modelsim simulation by disabling novopt
  • Use native VUnit argument parser instead of custom code
  • Optimize resource usage for olo_fix_cplx_mult
  • Improved license handling for AWS runner
  • Quantize input to all olo_fix bit-true models
  • Unify assertion messages in VHDL
    • Print related entity in all cases
    • Contributed by: obruendl
    • Reported by: lukileu
  • Update GitHub actions to use Node24
    • Required due to infrastructure changes on GitHub
    • Contributed by: obruendl

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • None

Reporters

Contributors

4.5.0

25-Apr-2026

Added Features

  • Added olo_base_sample_hold
    • Sample and hold component for bit-vectors
    • Contributed by: obruendl
  • Added olo_fix_sample_hold
    • Sample and hold component for fixed-point numbers
    • Contributed by: obruendl
  • Support Riviera Pro as simulator for running Open Logic regression tests
    • Contributed by: aruede
    • Note: This feature is NOT actively maintained by Open Logic due to the unavailability of a free or donated license
  • Added MaxPacketSize_g to olo_base_fifo_packet
    • Maximum packet size to accept for olo_base_fifo_packet (larger packets will be dropped)
    • Contributed by: tasgomes
  • Added Optimization_g generic to olo_base_fifo_packet
    • Optimize for clock speed (backwards compatibility) or for no stall cycles (new)
    • Contributed by: obruendl
    • Reported by: tasgomes
  • Added FeatureSet_g=DROP_SKIP_ONLY to olo_base_fifo_packet
    • Optimized implementation supporting dropping and skipping packets but not supporting repeating packets
    • Contributed by: obruendl
  • Added olo_fix_cplx_mult
    • Complex fixed-point multiplier with support for mixer operation
    • Contains 4-multiplier, 3-multiplier and TDM I/Q handling implementations
    • Contributed by: obruendl
  • Added olo_fix_cplx_addsub
    • Complex fixed-point adder/subtractor
    • Supports parallel and TDM I/Q handling
    • Contributed by: obruendl
  • Added olo_fix_madd
    • Multiply-add entity with optional pre-adder stage (used to build MACC chains e.g. for FIR filters)
    • Contributed by: obruendl

Backward Compatible Changes

  • Various documentation improvements
  • Added Code of Conduct

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fixinternal XY-Format for olo_fix_cordic_rot when IntXyFmt_g=AUTO
    • The format in VHDL did not match documentation and the python model
    • Reported by: abdomit

Reporters

Contributors

4.4.1

10-Mar-2026

Added Features

  • Added fixDynShift() function to olo_fix_pkg
    • Dynamically shift a fixed-point number by a variable amount of bits
    • Contributed by: obruendl

Backward Compatible Changes

  • None

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • MAke CORDIC (rotation and vecotring) synthesizable in Mode_g=Serial
    • Affected entities: olo_fix_cordic_rot, olo_fix_cordic_vect
    • The entities did fail synthesis with the setting Mode_g=Serial
    • Reported by: Niv Cohen

Reporters

Contributors

4.4.0

28-Feb-2026

Added Features

  • Added log2ceil() function for real values to olo_base_pkg_math
  • Added olo_fix_cic_dec_tdm
    • CIC decimator with time-division multiplexed input and output
    • Supports one or multiple channels
    • Contributed by: obruendl
  • Added olo_fix_cic_dec_par_tdm
    • CIC decimator with parallel input and time-division multiplexed output
    • Supports one or multiple channels
    • Contributed by: obruendl
  • Added olo_fix_pkg_writer
    • Python script to automatically generate VHDL packages and verilog headers to contain data from python
    • Used to pass parameters and number formats for fixed-point processing from Python to HDL
    • Contributed by: obruendl

Backward Compatible Changes

  • Update tools in CI Pipeline
    • Python 3.10 -> Python 3.13
    • GHDL 3.0.0 -> GHDL 4.1.0
    • NVC 1.13.3 -> NVC 1.19.0
    • VUnit 4.7.0 -> VUnit 5.0.0.dev7
  • Make all string generics case-insensitive
  • Allow InWidth_g=_OutWidth_g in olo_base_wconv_n2xn

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fix TX hanshaking issue in olo_intf_spi_slave
    • When Tx_Valid was asserted after Tx_Ready data was wrongly transferred
    • Reported by: borjarevuelta-tec

Reporters

Contributors

4.3.0

25-Jan-2026

Added Features

  • Added olo_fix_cordic_rot and olo_fix_cordic_vect
    • CORDIC algorithm for rotation and vectoring
    • Supports pipelined and serial modes
    • Contributed by: obruendl
  • Added olo_fix_bin_div
    • Binary divider for fixed-point numbers
    • Contributed by: obruendl
  • Added olo_base_latency_comp
    • Latency compensation component
    • Contributed by: obruendl

Backward Compatible Changes

  • Various documentation improvements
  • Initialization improvement for olo_base_cc_reset
    • Use reset value as initial value to improve synthesis on Altera Arria 10
    • Contributed by: LukiLeu
  • Improved resource control by adding more generics to olo_base_delay and olo_base_delay_cfg

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • None

Reporters

  • None

Contributors

4.2.0

09-Dec-2025

Added Features

  • Support for Yosys toolchain
    • Synthesis attributes
    • Addition of Yosys Cologne Chip synthesis to CI workflows
    • Script to import Open Logic
  • Support for Cologne Chip FPGAs
    • Yosys support (see above)
    • Addition of Cologne Chip synthesis to CI workflows
    • Tutorial
  • Added olo_base_rate_limit

Backward Compatible Changes

  • Improvement of scoped constraints (Vivado) for olo_intf_sync
  • Add optional byte-enables to olo_base_crc

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fix scooped constraints (Vivado) for olo_base_ram_sdp when implemented with distributed RAM
  • Fix half-bit-slip in olo_intf_uart depending on exact bit timing
    • Affected entities: olo_intf_uart
    • Reported by: jonpovey

Reporters

Contributors

4.1.0

13-Sep-2025

Added Features

  • Added scoped constraints for olo_base_ram_sdp to avoid timing violations being reported for implementation with distributed RAM
  • Added getSetBitIndex(), getLeadingSetBitIndex() and getTrailingSetBitIndex() functions to olo_base_pkg_logic for detecting first/last set bit in a std_logic_vector
  • Added olo_base_arb_wrr Weighted Round Robin Arbiter
  • Added runtime SCL frequency selection to olo_intf_i2c_master
  • Added DROP_ONLY mode to olo_base_fifo_packet
  • Added olo_base_crc_append
  • Added olo_base_crc_check

Backward Compatible Changes

  • Update to latest en_cl_fix content available from en_cl_fix
  • CI synthesis now also checks if there are any latches

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fix default value of Out_RstIn in olo_base_cc_status
  • Make AXI verification components multi-instance capable
    • Affected entities: olo_test_axi_master_vc, olo_test_axi_slave_vc
    • Contributed by: LukiLeu
  • Fix linter errors on Windows PCs

Reporters

Contributors

4.0.0

26-Jun-2025

Notes

Because the change to VHDL-2008 is non-reverse-compatible anyways, it was decided to put all pending non-reverse-compatible changes into 4.0.0. As a result no breaking changes are foreseen in near future after 4.0.0.

Added Features

  • Added scoped constraints for Vivado to FuseSoC packages.
  • Added compile_order.txt file to support compilation with any tool.
    • Input from the presentation at FDF25 at CERN
  • CI workflow to execute synthesis for every entity in Open Logic

Backward Compatible Changes

  • Various documentation improvements
  • Various smaller changes to the CI workflows

Non Backward Compatible Changes

  • Change language standard to VHDL-2008
    • All entities now must be compiled as VHDL-2008
    • Tool integrations are updated accordingly and will import Open Logic as VHDL-2008
    • Suggested action: Remove Open Logic from your project and re-add it using the tool integration scripts provided, see HowTo
  • Changed default generic values for olo_fix_round and olo_fix_saturate to round and saturate by default.
    • Affected entities: olo_fix_round, olo_fix_saturate
    • Reason: Instantiating those entities for NOT executing the corresponding operation (as it was the default before) does not make much sense.
  • Remove unused generics
    • olo_base_cam - removed RamBlockWidth_g
    • olo_base_prbs - removed deprecated LfsrWidth_g
    • olo_base_crc - removed CrcWidth_g
    • Reason: Code cleanup
  • Harmonized polynomial handling between olo_base_prbs and olo_base_crc
    • Affected entities: olo_base_crc
    • Polynomial_g, InitialValue_g and XorOutput_g are now std_logic_vector instead of natural
    • Reason: std_logic_vector allows for values wider than 32 bits. Using the same interface types for olo_base_crc and olo_base_prbs is easier to understand for users.
  • Change default value for UserTransactionSizeBits_g from 32 to 24 in olo_axi_master_full
    • Affected entities: olo_axi_master_full
    • Reason: Default values for UserTransactionSizeBits_g and AxiAddrWidth_g were incompatible (led to assertion failures)

Bugfixes (Backward Compatible)

  • Fix olo_base_delay_cfg for power of 2 MaxDelay_g values
    • Affected entities: olo_base_delay_cfg
  • Remove default values 'Z' from olo_intf_i2c_master ports because this led to synthesis errors with Microchip Libero
    • Affected entities: olo_intf_i2c_master
  • Removed In_Real port from olo_fix_from_real because not all tools accept it for synthesis, even if unused.
    • Affected entities: __olo_fix_from_real_
  • Fix needless olo_base_strobe_gen number range error and document rate limitations. Ranges are now actively checked by assertions.
    • Affected entities: __olo_base_strobe_gen_
    • Reported by: fpgauserdude

Reporters

Contributors

3.3.0

04-May-2025

Added Features

  • Various documentation improvements
  • Added fixed-point mathematics support based on en_cl_fix
    • Includes bit-true python models
    • Includes a tutorial for the fixed-point development flow
    • Entities added: olo_fix_abs, olo_fix_add, olo_fix_addsub, olo_fix_compare, olo_fix_from_real, olo_fix_limit, olo_fix_mult, olo_fix_neg, olo_fix_pkg, olo_fix_resize, olo_fix_round, olo_fix_saturate, olo_fix_sim_checker, olo_fix_sim_stimuli, olo_fix_sub, olo_fix_to_real
  • Added AWS CI runner for synthesis
    • Executes reference design test builds
    • Executes fusesoc test builds
  • Added support for VHDL_LS
    • Automatic generation of TOML file (see HowTo)
    • Allows advanced code-browsing in VSCode

Backward Compatible Changes

  • None

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • None

Reporters

Contributors

  • None

3.2.0

01-Apr-2025

Added Features

  • Added option to initialize RAM
    • Affected entities: olo_base_ram_tdp, olo_base_ram_sdp and olo_base_ram_sp

Backward Compatible Changes

  • Allow symbols width bigger than LFSR width in olo_base_prbs

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fixed RAM inference with byte-enables for Quartus Prime Standard

    • Affected entities: olo_base_ram_tdp, olo_base_ram_sdp and olo_base_ram_sp

  • Fixed RAM inference for Gowin EDA:

    • Affected entities: olo_base_ram_tdp

  • Fixed wrong wrong positive for assertions in olo_axi_master_simple

    • Only the assertion was changed, no synthesis relevant code was modified

    • Affected entites: olo_axi_master_simple, olo_axi_master_full

      Rreported by: rbrglez

Reporters

Contributors

3.1.0

27-Jan-2025

Added Features

  • Support for Gowin toolchain
    • Synthesis attributes
    • Script to import Open Logic
    • Tutorial
  • Added more functions to olo_base_pkg_logic
    • Added invertByteOrder()
    • Added greatestCommonFactor()
    • Added leastCommonMultiple()
  • Added olo_base_wconv_m2n
    • Arbitrary width converter (any input width to any output width)
  • Added olo_base_crc
    • CRC calculation engine
    • Can calculate multiple input bits per clock cycle

Backward Compatible Changes

  • Timing optimization for olo_base_fifo_async
    • General timing optimization to reach higher clock frequencies
    • Added generic to select between optimization for latency or speed
    • Reported by: svancau
  • Improved FuseSoC setup (#109)
    • Users can choose between local files or official releases
    • open-logic:open-logic:... for official release (downloaded from GitHub)
    • open-logic:open-logic-dev:... for local files
    • Reported by: rbrglez
  • Extracted attributes used by Open Logic into olo_base_pkg_attribute

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • None

Reporters

Contributors

  • None

3.0.2

01-Dec-2024

Added Features

  • None

Backward Compatible Changes

  • Added synchronous assertion to olo_base_reset_gen (#101)

    • Synchronous assertion is used for AsyncResetOutput_g=true
    • Number of synchronization stages is configurable through SyncStages_g

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fix reset CDC in olo_intf_clk_meas (#99)
    • Added proper reset CDC from Clk to ClkMeas
    • Reported by: tasgomes

Reporters

Contributors

  • None

3.0.1

26-Nov-2024

Added Features

  • Addition of Markdown linter to ensure adherence to markdown conventions (#93)

Backward Compatible Changes

  • Improve linter configuration
    • Workaround for procedures and functions without arguments was removed
  • Improvements on VSCode integration

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fix olo_axi_master_simple for AxiAddrWidth_g < log2(AxiMaxBeats_g+1) (#87)

Reporters

Contributors

3.0.0

28-Oct-2024

Added Features

  • Microchip Libero integration
    • Script to automatically import all Open Logic features into a Libero project
    • Libero tutorial (see LiberoTutorial)
  • Addition of VSG linter to ensure adherence to coding conventions (#43)
  • VSCode integration of VSG linter and VUnit simulation
    • See HowTo for documentation about how to use it
  • Extension of CI workflow
    • Addition of VSG linting
    • Addition of job to aggregate all results and report them in the GitHub Pull-Request

Backward Compatible Changes

  • Various documentation improvements
  • Addition of generic to configure number of synchronization stages in all clock-crossings. This allows satisfying very high MTBF requirements.
    • Modified entities: olo_base_cc... and _olo_base_fifo_async

Non Backward Compatible Changes

All entities are backward compatible. Non backward compatible changes were applied to packages only.

  • Modifications to packages to follow coding conventions.
    • Affected entities: olo_base_pkg_array, , _olo_axi_pkg_protocol, olo_intf_i2c_master_pkg
  • Removal of reducing logic functions from olo_base_pkg_logic (#85)
    • The reducing logic functions from ieee.std_logic_misc shall be used instead
    • Reported by: andkae

Bugfixes (Backward Compatible)

  • Fix heap-size issue for NVC simulator

Reporters

Contributors

2.3.1

16-Oct-2024

Added Features

  • None

Backward Compatible Changes

  • None

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • CRITICAL - Fix wrong clock crossing in olo_base_fifo_async (#79)

Reporters

Contributors

  • None

2.3.0

27-Sep-2024

Added Features

  • Implement synthesis attributes for Synplify based tools
    • Examples of Synplify based toolchains: Lattice ICECube, Microchip
  • Setup of Github Sponsors profile for funding the project
  • olo_base_packet_fifo
    • Store and forward packet FIFO
    • Allows to drop packets while writing them (even after some data was written)
    • Allows skipping and repeating packets when reading them
  • olo_intf_uart
    • UART interface
  • olo_base_decode_firstbit
    • Timing optimal first-bit decoder
  • olo_base_cam
    • Content addressable memory
  • olo_base_strobe_gen
    • Added fractional mode - dynamically extend/shorten period by one clock cycle to meet the requested average strobe frequency.

Backward Compatible Changes

  • Various documentation improvements
  • olo_intf_spi_slave
    • Suppress needless MISO toggling at the end of a transaction (#68, reported by betocool-prog )

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fixed documentation of olo_intf_spi_slave.
    • Maximum SCLK frequency is 8x lower than Clk frequency (not 6x)

Credits

Reporters

Contributors

  • None

2.2.0

04-Sep-2024

Added Features

  • Support for NVC Simulator
    • NVC simulator can be started passing the argument "--nvc" to the run.py
    • Added NVC simulator to CI scripts
    • Co-authored by nickg
  • Questa integration
    • Script to automatically compile all Open Logic features in Questa
    • Questa tutorial (VHDL and Verilog)
  • Addition of to01() functions to olo_base_pkg_logic
  • olo_intf_spi_slave
    • SPI slave
  • olo_base_cc_handshake
    • Clock crossing with fully Read/Valid handshake but without need for distributed RAM (in contrast to olo_base_fifo_async)

Backward Compatible Changes

  • Various documentation improvements
    • Clarification regarding omission of ID signals in olo_axi_master..._ (#50, contributed by kuriousd )
    • Remove duplicated Ready signal from figures in Conventions (#54, reported by tasgomes )
  • Various optimizations on the CI/CD infrastructure
  • Reduction of the latency of olo_base_cc_pulse by one clock cycle

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • None

Credits

Reporters

Contributors

2.1.0

30-Jul-2024

Added Features

  • Efinix Efinity integration
    • Script to automatically import all Open Logic features into an Efinity project
    • Addition of synthesis attributes for Efinity
    • Efinity tutorial
  • Added FuseSoC package manager support
  • olo_intf_spi_master
    • SPI master

Backward Compatible Changes

  • Various documentation improvements
  • Various optimizations on the CI/CD infrastructure

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fixed sensitivity list in olo_axi_master_simple (#41)
    • M_Axi_RResp was missing
    • Credits to kuriousd for reporting
  • Process scoped constraints late for AMD Vivado
    • User constraints must be processed before scoped constraints, otherwise clocks are not known to scoped constraints

Credits

Reporters

Contributors

  • None

2.0.0

06-Jul-2024

Added Features

  • Altera Quartus integration
    • Script to automatically import all Open Logic features into a Quartus project
  • Added tutorials
    • Vivado Verilog tutorial
    • Quartus VHDL tutorial
    • Quartus Verilog tutorial
  • olo_base_reset_gen
    • Reset generator (and synchronizer)
  • olo_base_flowctrl_handler
    • Allows to add flow-control (ready) around entities without flow-control (valid only)

Backward Compatible Changes

  • Various documentation improvements

Non Backward Compatible Changes

  • Removed t_aslv (array of unconstrained std_logic_vector) from olo_base_pkg_array
    • Arrays of unconstrained types are not accepted by Quartus

Bugfixes (Backward Compatible)

  • None

1.2.0

27-Jun-2024

Added Features

  • AMD Vivado integration
    • Script to automatically import all Open Logic features into a Vivado project
    • Vivado tutorial
  • olo_intf_clk_meas
    • Measure the frequency of a clock signal (based on a clock with a known frequency)
  • olo_intf_debounce
    • Debouncing for external signals (e.g. inputs from switches or buttons)

Backward Compatible Changes

  • Various documentation improvements
  • Execute scoped constraint scripts in separate namespaces
    • This avoids unwanted interactions between the script through global variables

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Fix scoped constraints for olo_intf_sync
    • Incomplete input delays were reported before the fix
  • Fix inconsistencies of olo_intf_i2c_master generic default values compared to documentation
    • There was a mismatch for CmdTimeout_g
    • ClkFrequency_g had a default value in the implementation before the change (which is wrong because the clock is specific to the design)

1.1.0

15-Jun-2024

Added Features

  • olo_intf_i2c_master
    • I2C master
    • Multi-Master and clock-stretching capable
  • olo_intf_sync
    • Double stage synchronizer for asynchronous external signals
    • Includes scoped timing constraints
  • olo_axi_master_full
    • AXI Master with support for unaligned and odd-sized transfers (other sizes than multiple of AXI words)

Backward Compatible Changes

  • Various documentation improvements
  • Added Rd_Last signal to olo_axi_master_simple to simplify handling of read-data.
  • olo_base_wconv_n2xn now supports InWidth=OutWidth

Non Backward Compatible Changes

  • None

Bugfixes (Backward Compatible)

  • Change default UserTransactionSizeBits_g in olo_axi_master_simple to 24 bits
    • The combination of default values before was illegal
    • Backwards compatible because the default values had to be overwritten for successful compilation before the change anyways.
  • Change default values of AlmFullLevel_g and AlmEmptyLevel_g to 0
    • Using another generic (Depth_g) as default value for generics is illegal.
    • Backwards compatible because the default values had to be overwritten for successful compilation before the change anyways.
  • Fix AxiDataWidth_g related assertions in olo_axi_lite_slave
    • Backwards compatible because the change only adds error messages for anyways illegal generics combinations

1.0.0

31-May-2024

First release

Added Features

n/a

Backward Compatible Changes

n/a

Non Backward Compatible Changes

n/a

Bugfixes (Backward Compatible)

n/a

0.x.x

All 0.x.x releases are considered early stage development and not documented in detail.