olo_base_prbs¶
Status Information¶
VHDL Source: olo_base_prbs
Description¶
This component generates a pseudorandom binary sequence based (PRBS) on a logic feed-back shift register (LFSR) method. A set of common polynomials (aiming the maximum cycle possible) is available in olo_base_pkg_logic and can be passed to olo_base_prbs through the generic Polynomial_g.
The number of bits per symbol which is presented at the output is configurable.
Polynomials are passed as std_logic_vector where a one denotes every position where x^n is used: "100010000" means "x⁹ +x⁵ + 1".
The initial state of the LFSR can be configured throuh Seed_g at compile time or through State_New at the moment where State_Set='1' is asserted at runtime. Note that the state of an LFSR never should be zero - otherwise the LFSR will stay zero forever.
Note that for the case of BitsPerSymbol_g > width(Polynomial_g) the LFSR is shifted before the first symbol is produced. Hence Seed_g (after reset) resp. State_New (after setting the state) is ocurring in the highest bits of the first Out_Data word - and the lower bits are the first results of the LFSR calculation.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| Polynomial_g | std_logic_vector | - | Polynomial to use. "100010000" means "x⁹+x⁵+1". |
| Seed_g | std_logic_vector | - | Initial state of the LFSR. Needs to be the same width as Polynomial_g. Must be non-zero vector. |
| BitsPerSymbol_g | positive | 1 | Number of bits of the PRBS sequence to present at the output for every symbol (width of Out_Data). Must be at least 1. |
For new designs, LfsrWidth_g shall be left unassigned.
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Data | out | BitsPerSymbol_g | - | Output data |
| Out_Valid | out | 1 | - | AXI4-Stream handshaking signal for Out_Data Always one. The output is always valid. |
| Out_Ready | in | 1 | '1' | AXI4-Stream handshaking signal for Out_Data |
State¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| State_Current | out | width of Polynomial_g | - | Current state of the LFSR register |
| State_Set | in | 1 | '0' | The LFSR content is set to State_New when State_Set='1' is asserted. |
| State_New | in | width of Polynomial_g | 0 | LFSR state to set upon State_Set='1'. |
Note: If the state functionality is not needed, the corresponding signals can be left unconnected.
Architecture¶
The PRBS generation is implemented using an LFSR register.
Below figures shows the implementation for a 4-bit LFSR with the polynomial x⁴ + x³ + 1 ("1100").
