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olo_ft_fifo_sync

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Status Information

VHDL Source: olo_ft_fifo_sync

Description

This component implements an ECC-protected synchronous FIFO using SECDED (Single Error Correction, Double Error Detection) Hamming code. The interface and behavior match olo_base_fifo_sync.

The ECC is transparent to the user: data is automatically encoded on write and decoded/corrected on read. Error status flags indicate whether a single-bit error was corrected or a double-bit error was detected.

Generics

Name Type Default Description
Width_g positive - Number of data bits per FIFO entry. The internal FIFO is wider to accommodate ECC parity bits.
Depth_g positive - Number of entries the FIFO has
AlmFullOn_g boolean false Enable almost-full flag
AlmFullLevel_g natural 0 Almost-full threshold level
AlmEmptyOn_g boolean false Enable almost-empty flag
AlmEmptyLevel_g natural 0 Almost-empty threshold level
RamStyle_g string "auto" Controls the RAM implementation resource
RamBehavior_g string "RBW" Controls the RAM behavior. "RBW" or "WBR"
ReadyRstState_g std_logic '1' Value of In_Ready during reset. Behaves exactly as in olo_base_fifo_sync.

Interfaces

Clock and Reset

Name In/Out Length Default Description
Clk in 1 - Clock
Rst in 1 - Reset (high-active, synchronous to Clk). Empties the FIFO and clears the internal error-injection latch.

Input Data

Name In/Out Length Default Description
In_Data in Width_g - Input data
In_Valid in 1 '1' Input valid (AXI-S handshaking)
In_Ready out 1 N/A Input ready (AXI-S handshaking)
In_Level out ceil(log2(Depth_g+1)) N/A Input-side fill level

Output Data

Name In/Out Length Default Description
Out_Data out Width_g N/A Output data (corrected if a single-bit error was detected)
Out_Valid out 1 N/A Output valid (AXI-S handshaking)
Out_Ready in 1 '1' Output ready (AXI-S handshaking)
Out_Level out ceil(log2(Depth_g+1)) N/A Output-side fill level
Out_EccSec out 1 N/A Single error corrected flag. Time-aligned with Out_Data.
Out_EccDed out 1 N/A Double error detected flag. Read data is unreliable. Time-aligned with Out_Data.

Status

Name In/Out Length Default Description
Full out 1 N/A FIFO is full
AlmFull out 1 N/A FIFO is almost full
Empty out 1 N/A FIFO is empty
AlmEmpty out 1 N/A FIFO is almost empty

Error Injection (optional)

These ports drive the internal olo_ft_ecc_encode instance. Leave them unconnected for normal operation; see Open Logic Fault-Tolerance Principles - Error Injection for the latched-strobe semantics shared across the ft area.

Name In/Out Length Default Description
In_ErrInj_BitFlip in eccCodewordWidth(Width_g) all 0 Codeword-wide flip pattern. Each '1' bit XORs (flips) the corresponding bit of the stored codeword. Popcount 1 = SEC-correctable, popcount 2 = DED-detectable.
In_ErrInj_Valid in 1 '0' Strobe that latches In_ErrInj_BitFlip into the encoder's pending-injection register. The latched pattern is applied to the next accepted input beat.

Detailed Description

Architecture

olo_ft_fifo_sync architecture

The entity is composed of three Open Logic entities:

  1. olo_ft_ecc_encode encodes each accepted input beat into a SECDED codeword.
  2. olo_base_fifo_sync stores the codeword (entity configured with a codeword-wide word). All levels and status flags come directly from it.
  3. olo_ft_ecc_decode decodes and corrects each beat on the read side and drives Out_EccSec / Out_EccDed time-aligned with Out_Data.

The codeword is protected end-to-end while it is inside the FIFO: encoding happens before, and decoding after, all storage elements.

See olo_base_fifo_sync for detailed FIFO behavior.

Note that the ECC FIFOs deliberately come without a scrubber, unlike the ECC RAMs (olo_ft_ram_sp_scrub, olo_ft_ram_sdp_scrub). A FIFO does not store data permanently, so as long as it is drained regularly, errors do not accumulate in a word over time and there is nothing for a background scrubber to repair.

Combinational ECC Encoder and Decoder

Both codecs are instantiated with Pipeline_g = 0. The datapath to and from the internal FIFO is therefore combinational, and the ft entity behaves exactly like its olo_base_fifo_sync counterpart.

The ECC decode lies between the RAM output and the output ports and is the critical path of the entity. Where it limits the clock frequency, use olo_base_fifo_sync directly and place registered olo_ft_ecc_encode / olo_ft_ecc_decode instances around it in the surrounding design. The levels and status flags of the base FIFO then do not account for the beats held in the codec pipelines.

ECC Overhead, Error Injection and Status Flags

See the corresponding sections in Open Logic Fault-Tolerance Principles:

Constraints

See Open Logic Fault-Tolerance Principles - Constraints That Apply Across the Area for the constraints that apply across the ft area. No additional olo_ft_fifo_sync-specific constraints apply.