olo_fix_cplx_mult¶
Status Information¶
VHDL Source: olo_fix_cplx_mult
Bit-true Model: olo_fix_cplx_mult
Description¶
This entity performs multiplication of two complex fixed-point numbers.
The entity also can be configured to operate as mixer (complex to complex) by selection Mode_g=MIX. In mixer mode the imaginary part of In_B is inverted.
I (in-phase) and Q (quadrature-phase) can be handled parallel or TDM.
For IqHandling_g=Parallel, a 3 (Implementation_g=MULT3) or 4 (Implementation_g=MULT4) multiplier architecture can be chosen.
For IqHandling_g=TDM, an architecture exploiting the time-multiplexing of I and Q samples is implemented, which requires only 2 multipliers.
Latency The latency of this entity heavily depends on the configuration but it is constant for any generic configuration. See detailed calculations in the Detail section below.
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| Mode_g | string | "MULT" | Operation mode: "MULT" - complex multiplication "MIX" - Complex to complex mixer |
| Implementation_g | string | "MULT3" | Multiplier architecture for Mode_g=MULT "MULT3": 3 multipliers "MULT4": 4 multipliers (k1=ac, k2=bd, k3=ad, k4=bc) |
| IqHandling_g | string | "Parallel" | "Parallel" - I/Q arrive in parallel, ports InA_I and InA_Q are used "TDM" - I/Q arrive TDM, ports InA_IQ and InB_IQ are used |
| AFmt_g | string | - | Input A format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| BFmt_g | string | - | Input B format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| ResultFmt_g | string | - | Format of the result String representation of an en_cl_fix Format_t (e.g. "(0,1,15)") |
| Round_g | string | "Trunc_s" | Rounding mode String representation of an en_cl_fix FixRound_t. |
| Saturate_g | string | "Warn_s" | Saturation mode String representation of an en_cl_fix FixSaturate_t. |
| MultRegs_g | natural | 1 | Number of pipeline stages for the multiplication |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| InA_I | in | width(AFmt_g) | - | Input data A in-phase for IqHandling_g=Parallel Format: AFmt_g |
| InA_Q | in | width(AFmt_g) | - | Input data A quadrature-phase for IqHandling_g=Parallel Format: AFmt_g |
| InA_IQ | in | width(AFmt_g) | - | Input data A for IqHandling_g=TDM Format: AFmt_g |
| InB_I | in | width(BFmt_g) | - | Input data B in-phase for IqHandling_g=Parallel Format: BFmt_g |
| InB_Q | in | width(BFmt_g) | - | Input data B quadrature-phase for IqHandling_g=Parallel Format: BFmt_g |
| InB_IQ | in | width(BFmt_g) | - | Input data B for IqHandling_g=TDM Format: BFmt_g |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for InA and InB |
| In_Last | in | 1 | '0' | Used for optional TDM synchronization for IqHandling_g=TDM. |
When used as a mixer, InA is the signal to be mixed and InB is the mixing frequency.
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_I | out | width(ResultFmt_g) | N/A | Result data in-phase for IqHandling_g=Parallel Format ResultFmt_g |
| Out_Q | out | width(ResultFmt_g) | N/A | Result data quadrature-phase for IqHandling_g=Parallel Format ResultFmt_g |
| Out_IQ | out | width(ResultFmt_g) | N/A | Result data for IqHandling_g=TDM Format ResultFmt_g |
| Out_Valid | out | 1 | N/A | AXI-S handshaking signal for Out_Result |
| Out_Last | out | 1 | N/A | Used for optional TDM synchronization for IqHandling_g=TDM. |
Detail¶
4 Multiplier IQ-Parallel Architecture¶
This architecture is implemented when:
- Implementation_g="MULT4"
- IqHandling_g="Parallel"
This is the most straightforward architecture. It implements the following mathematics:
A = (a + bi)
B = (c + di)
Re = a x c - b x d
Im = a x d + b x c
The figure below shows the architecture. It is optimized for mapping into Multiply-Add DSP blocks.
Note that for Mode_g=MULT the black operations apply. For Mode_g=MIX the red operations apply, which corresponds to inverting the imaginary part of InB.
Latency This architecture has a latency of MultRegs_g+ 3 + resize_latency clock cycles.
Where resize_latency is calculated as follows:
- +1 cycle if Round_g is NOT "Trunc_s"
- +1 cycle if Saturate_g is NOT "None_s"/"Warn_s"
3 Multiplier IQ-Parallel Architecture¶
This architecture is implemented when:
- Implementation_g="MULT3"
- IqHandling_g="Parallel"
This architecture does save one multiplier at the cost of more adders and a more complex routing. It implements the following mathematics:
A = (a + bi)
B = (c + di)
k1 = c x (a + b)
k2 = a x (d - c)
k3 = b x (c + d)
Re = k1 - k3
Im = k1 + k2
The figure below shows the architecture.
Important: Some synthesis tools require an increased MultRegs_g to really implement it with 3 multipliers. If you see 4 multipliers being implemented, try increasing MultRegs_g. The architecture depicted nicely fits into 3 multiply-add elements (indicated by colors in the figure).
Latency This architecture has a latency of MultRegs_g+ 5 + resize_latency clock cycles.
Where resize_latency is calculated as follows:
- +1 cycle if Round_g is NOT "Trunc_s"
- +1 cycle if Saturate_g is NOT "None_s"/"Warn_s"
TDM Architecture¶
This architecture is implemented when:
- IqHandling_g="TDM"
It does implement the same mathematics as the 4 multiplier architecture, but I and Q are handled in a time-multiplexed manner. As a result, only two multipliers are needed and selecting between I and Q samples can also happen by a delay of a clock cycle instead of a multiplexer.
The Last signal MUST be applied on Q samples only because I is the first sample in a pair and therefore cannot be the last of a TDM burst. I samples with Last='1' will be ignored and used for I/Q resynchronization (the first sample after will be interpreted as the first I sample of the next TDM burst).
Note that for Mode_g=MULT the black operations apply. For Mode_g=MIX the red operations apply, which corresponds to inverting the imaginary part of InB.
Latency This architecture has a latency of MultRegs_g+ 4 + resize_latency clock cycles. The latency applies from input of the Q sample to output of the Q sample. The I sample latency is not constant because the I output can only be produced after the Q sample has been received on the input side.
Where resize_latency is calculated as follows:
- +1 cycle if Round_g is NOT "Trunc_s"
- +1 cycle if Saturate_g is NOT "None_s"/"Warn_s"