olo_fix_compare¶
Status Information¶
VHDL Source: olo_fix_compare Bit-true Model: olo_fix_compare
Description¶
This entity performs a comparison of two fixed-point numbers. The comparison to execute can be selected through generics.
Input A is on the left hand side of the operator, Input B on the right hand side. E.g. for Comparison_g=">", the comparison implemented is A > B.
Latency of this entity is OpRegs_g. The default generics lead to a latency of 1 clock cycle.
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| AFmt_g | string | - | Input A format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| BFmt_g | string | - | Input B format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| Comparison_g | string | - | Comparison to execute. Selection: >, <, =, !=, >=, <= |
| OpRegs_g | natural | 1 | Number of pipeline stages for the operation |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | '0' | Clock Not required if all registers are disabled (OpRegs_g=0) |
| Rst | in | 1 | '0' | Reset input (high-active, synchronous to Clk) Not required if all registers are disabled (OpRegs_g=0) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_A | in | width(AFmt_g) | - | Input data Format: AFmt_g |
| In_B | in | width(BFmt_g) | - | Input data Format: BFmt_g |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for In_A and In_B |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Result | out | 1 | N/A | '1' = true, '0' = false' |
| Out_Valid | out | 1 | N/A | AXI-S handshaking signal for Out_Result |
Detail¶
No detailed description required. All details that could be mentioned here are already covered by fixed point principles.