olo_fix_mix_c2r¶
Status Information¶
VHDL Source: olo_fix_mix_c2r
Bit-true Model: olo_fix_mix_c2r
Description¶
This entity implements a complex-to-real mixer. It multiplies a complex input signal (In_SigI, In_SigQ) with a complex local oscillator (In_MixI, In_MixQ) to produce a real output signal (Out_SigReal).
The downconversion convention is used, which corresponds to multiplying by the conjugate of the local oscillator:
Out_SigReal = +In_SigI x In_MixI + In_SigQ x In_MixQ
Two I/Q handling modes are supported, selected by the IqHandling_g generic:
- Parallel -- I and Q channels of both signal and mixer are presented simultaneously on separate ports. Two multiply-accumulate operations run in parallel.
- TDM -- I sample is followed immediately by Q sample on shared ports (In_SigIQ, In_MixIQ). One multiplier is time-shared between the I and Q products; one real output sample is produced per I/Q pair.
The In_Last port is used in TDM mode to re-synchronise the I/Q phase: after In_Last is asserted the first sample received is treated as I. In Parallel mode In_Last is ignored.
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| InFmt_g | string | - | Input signal format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| MixFmt_g | string | - | Local oscillator format String representation of an en_cl_fix Format_t (e.g. "(1,0,15)") |
| OutFmt_g | string | - | Output format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| Round_g | string | "Trunc_s" | Rounding mode String representation of an en_cl_fix FixRound_t. |
| Saturate_g | string | "Warn_s" | Saturation mode String representation of an en_cl_fix FixSaturate_t. |
| MultRegs_g | natural | 1 | Number of pipeline stages for the multiplication |
| IqHandling_g | string | "Parallel" | I/Q handling mode: "Parallel" or "TDM" |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for all inputs |
| In_SigI | in | width(InFmt_g) | (all zeros) | Signal in-phase component for IqHandling_g="Parallel" Format: InFmt_g |
| In_SigQ | in | width(InFmt_g) | (all zeros) | Signal quadrature component for IqHandling_g="Parallel" Format: InFmt_g |
| In_MixI | in | width(MixFmt_g) | (all zeros) | Oscillator in-phase component for IqHandling_g="Parallel" Format: MixFmt_g |
| In_MixQ | in | width(MixFmt_g) | (all zeros) | Oscillator quadrature component for IqHandling_g="Parallel" Format: MixFmt_g |
| In_SigIQ | in | width(InFmt_g) | (all zeros) | Signal I then Q for IqHandling_g="TDM" Format: InFmt_g |
| In_MixIQ | in | width(MixFmt_g) | (all zeros) | Oscillator I then Q for IqHandling_g="TDM" Format: MixFmt_g |
| In_Last | in | 1 | '0' | TDM re-sync: marks the last Q sample; the next sample is treated as I |
In_Valid is the single handshaking signal for all inputs. Ready is not supported; the entity accepts data every cycle In_Valid is asserted.
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Valid | out | 1 | - | AXI4-Stream handshaking signal for Out_SigReal |
| Out_SigReal | out | width(OutFmt_g) | - | Real output Format: OutFmt_g |
In TDM mode, one output sample is produced per I/Q input pair, so the output rate is half the input sample rate.
Detail¶
Parallel Architecture¶
The parallel architecture uses two multiply-accumulate operations whose structure matches the I-path of olo_fix_cplx_mult in MULT4/Parallel/MIX mode.
Latency This architecture has a latency of MultRegs_g+ 3 + resize_latency clock cycles.
Where resize_latency is calculated as follows:
- +1 cycle if Round_g is NOT "Trunc_s"
- +1 cycle if Saturate_g is NOT "None_s"/"Warn_s"
TDM Architecture¶
The TDM architecture time-shares a single multiplier between the I and Q products, following the same pipeline as olo_fix_cplx_mult in TDM/MIX mode but producing only the real output.
The In_Last signal (sampled on the Q slot) resets the I/Q phase tracker so that the immediately following sample is treated as I. This mirrors the resync behaviour of olo_fix_cplx_mult.
Latency (TDM): MultRegs_g + 3 clock cycles from the I input sample, plus one cycle each for rounding and saturation when those registers are enabled.
The latency is defined as Q-sample input to real output.