olo_base_ram_sdp¶
Status Information¶
VHDL Source: olo_base_ram_sdp
Description¶
This component implements a simple dual-port RAM. It offers separate read and write ports.
By default read and write port both run on the same clock but optionally the implementation with separate read/write clocks is supported.
The RAM is implemented in pure VHDL but in a way that allows tools to implement it in block-RAMs.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| Depth_g | positive | - | Number of addresses the RAM has |
| Width_g | positive | - | Number of bits stored per address (word-width) |
| UseByteEnable_g | boolean | false | By default, all bits of a memory cell are written. Enabling byte-enables allows to control which bytes are written individually. The setting is only allows for if Width_g is a multiple of eight (otherwise the word byte-enable does not make sense). Note that setting this setting to true can lead to increased resource usage. See Detailed Description |
| IsAsync_g | boolean | false | By default read- and write-port both use the samle clock Clk. By settings IsAsync_g=true, an asynchronous RAM is implemented where the write-port use Clk and the read-port uses Rd_Clk. |
| RdLatency_g | positive | 1 | Read latency. 1 is the behavior of a normal synchronous RAM Higher values can be desirable for timing-optimization in high-speed logic. |
| RamStyle_g | string | "auto" | Through this generic, the exact resource to use for implementation can be controlled. This generic is applied to the attributes ram_style and ramstyle which vendors offer to control RAM implementation. Commonly used values are given below. AMD: "auto", block", "distributed", "ultra" - see ug901 for details Intel: "M4K", "M9K", "M20K", "M144K", "MLAB" - see quartus-help for details Efinix: "block_ram", "registers" - see efinity-synthesis for details Synplify(Lattice/Microchip): "block_ram", "registers", "distributed" - see microchip-attributes-guide for details Gowin: "block_ram", "distributed_ram", "registers", "rw_check", "no_rw_check" - see GowinSynthesis User Guide for details. |
| RamBehavior_g | string | "RBW" | Controls the RAM behavior. Must match the behavior of RAM resources of the target technology for efficient implementation. "RBW": Read-before-write - more common common, hence the default "WBR": Write-before-read If you are unsure what behavior your target device offers, try both settings and check which one is correctly mapped to RAM resources using the synthesis report. |
| InitString_g | string | "" | Initialization data for the memory formatted as comma separated list of hex calues (e.g. "0x1234, 0x0ABC"). Each value MUST have the 0x prefix. The first value goes to address 0, the second one to address 1 and so on. |
| InitFormat_g | string | "NONE" | "NONE": RAM is not initialized "HEX": RAM is initialized with InitString_g interpreted as list of hex values. Note: Not all technologies support RAM initialization. Check the documentation of your technology/tools for details. |
For some technologies, _RamBehavior_g="WBR" must be used to allow mapping RAM to distributed memory. It's best to verify correct mappping by a quick test-synthesis with the target toolchain.
Interfaces¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | '0' | Reset synchronous to Clk - Only used if IsAsync_g=false Optional, only resets internal state of Rd_Valid Does NOT reset the content of memory cells! |
| Wr_Addr | in | ceil(log2(Depth_g)) | - | Write address |
| Wr_Be | in | Width_g/8 | All '1' | Byte-enables Ignored if UseByteEnable_g = false |
| Wr_Ena | in | 1 | '1' | Write enable. The memory cell at Wr_Addr is written only if Wr_Ena='1'. |
| Wr_Data | in | Width_g | - | Write data |
| Rd_Clk | in | 1 | '0' | Read-clock - Only used if IsAsync_g=true, otherwise Clk is used for the read-port. |
| Rd_Rst | in | 1 | '0' | Read-reset synchronous to Rd_Clk - Only used if IsAsync_g=true Optional, only resets internal state of Rd_Valid Does NOT reset the content of memory cells! |
| Rd_Addr | in | ceil(log2(Depth_g)) | - | Read address |
| Rd_Ena | in | 1 | '1' | Read enable. When asserted, Rd_Data is updated and Rd_Valid is asserted after RdLatency_g cycles. Synchronous to Clk if IsAsync_g=false, otherwise synchronous to Rd_Clk |
| Rd_Data | out | Width_g | N/A | Read data |
| Rd_Valid | out | 1 | N/A | Read valid. Asserted RdLatency_g cycles after Rd_Ena was asserted. Synchronous to Clk if IsAsync_g=false, otherwise synchronous to Rd_Clk |
Detailed Description¶
Read Latency¶
Below figure explains the RdLatency_g generic in detail:
Byte Enables¶
Due to tool limitations regarding inference, the usage of byte enables (UseByteEnable_g=true) can lead to increased RAM usage.nTherefore, do not use byte enable signals unless this is strictly required.
Open Logic internally does not use byte enables, hence only users using the olo_base_ram_sdp component directly with byte-enables enabled are affected.
For applications where vendor/tool independence is important, this is to be regarded as a required trade-off. For applications that target only one specific technology, it is suggested to use vendor macros if RAM with byte enables if required.
Rd_Ena and Rd_Valid¶
The RAM is read and Rd_Data is updated only when Rd_Ena signal is asserted.
Besides controlling RAM read operations, the Rd_Ena signal controls the Rd_Valid signal. This means that if Rd_Ena is asserted, Rd_Valid is asserted after RdLatency_g cycles, indicating that the data on Rd_Data is valid and can be used. This is very useful in pipelined design, especially with configurable RdLatency_g values because it allows to design logic around independently of the RAM read latency.
