olo_base_reset_gen¶
Status Information¶
VHDL Source: olo_base_reset_gen
Description¶
This component generates reset pulses of a specified minimum duration after FPGA configuration and optionally upon request (reset input).
The component does guarantee synchronous de-assertion of the reset. Assertion is asynchronous or synchronous, depending on the users choice.
Note: Because the reset input is detected asynchronously, it is important that this input is glitch-free.
The block comes with automatic constraints. For manual constraining, a set_max_delay -datapath_only or a
set_false_path constraint is required for the RstIn input (if it is used).
Note: Automatic constraining currently only works for AMD tools (Vivado). Manual constraints are required for other tools.
Note: For using Open Logic from in Vivado, manual constraints are required for Versions prior to 2024.2. Automatic constraining currently only works for verilog only since 2024.2.
WARNING: Reset assertion upon FPGA configuration relies on the target technology supporting specific FF initialization state. For the most common target technologies (namely AMD and altera) this is given. However, for technologies which do not support specifying FF initialization state (e.g. Microchip devices) an external reset signal must be connected to RstIn - RstOut will not be asserted upon FPGA configuration. If in doubt, refer to the the documentation of your target technology or play it safe and connect RstIn.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| RstPulseCycles_g | positive | 3 | Minimum duration of the reset pulse in clock cycles Range: 3 ... 2^31-1 |
| RstInPolarity_g | std_logic | '1' | Polarity of RstIn. '1' - Active High '0' - Active Low |
| AsyncResetOutput_g | boolean | false | True = RstOut is asserted asynchronously (RstIn is forwarded even in absence of Clk activity) False = RstOut may is asserted synchronously (upon Clk rising edge). |
| SyncStages_g | positive | 2 | Number of synchronization stages for the multi-stage synchronizer in case of AsyncResetOutput_g=false. This generic is not having any effect for AsyncResetOutput_g=true. Range: 2 ... 4 |
Interfaces¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| RstOut | out | 1 | - | Reset output (high-active, synchronous to Clk) Note: The output is always high-active according to Open Logic guidelines. |
| RstIn | in | 1 | not RstInPolarity_g | Reset input. The reset is detected asynchronously - any glitches on this signal lead to a reset pulse being generated. The input is optional. If reset shall only be asserted after FPGA configuration, it can be left floating (limited to target technologies supporting specifying the FF initialization state). |
Architecture¶
The architecture of the block for AsyncResetOutput_g=false is shown in the figure below:
The reset is detected asynchronously. If the RstIn input matches RstInPolarity_g, the reset synchronizer FFs are asynchronously set. The reset assertion is then synchronized using a multi-stage synchronizer. A synchronous counter is then used to prolong the reset pulse to the required duraton.
The architecture for AsyncResetOutput_g=true is relatively similar, just with the last (metastability remover) FF in the synchronizer chain being omitted. Additionally, because the synchronous counter asserts its reset output only upon Clk edges, an additional OR (red) is added at the output.
