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olo_fix_saturate

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Status Information

VHDL Source: olo_fix_saturate
Bit-true Model: olo_fix_saturate

Description

This entity allows reducing the number of integer bits in a fixed-point number and executes saturation.

Note: The output format MUST be one that ONLY requires saturation. It is not allowed to select any other number of fractional bits than the input format has.

Latency of this entity is given by the optional saturation register. The default generics lead to a latency of 1 clock cycle.

For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.

Generics

Name Type Default Description
AFmt_g string - Input A format
String representation of an en_cl_fix Format_t (e.g. "(1,1,15)")
ResultFmt_g string - Format of the result
String representation of an en_cl_fix Format_t (e.g. "(0,1,15)")
Saturate_g string "Sat_s" Saturation mode
String representation of an en_cl_fix FixSaturate_t.
SatReg_g string "YES" Presence of saturation pipeline stage
"YES": Always implement register
"NO": Never implement register
"AUTO": Implement register if saturation is needed according to the formats chosen

Interfaces

Control

Name In/Out Length Default Description
Clk in 1 '0' Clock
Not required if all registers are disabled (SatReg_g="NO")
Rst in 1 '0' Reset input (high-active, synchronous to Clk)
Not required if all registers are disabled (SatReg_g="NO")

Input Data

Name In/Out Length Default Description
In_A in width(AFmt_g) - Input data
Format: AFmt_g
In_Valid in 1 '1' AXI4-Stream handshaking signal for In_A

Output Data

Name In/Out Length Default Description
Out_Result out width(ResultFmt_g) N/A Result data
Format ResultFmt_g
Out_Valid out 1 N/A AXI-S handshaking signal for Out_Result

Detail

No detailed description required. All details that could be mentioned here are already covered by fixed point principles.