olo_fix_mult¶
Status Information¶
VHDL Source: olo_fix_mult
Bit-true Model: olo_fix_mult
Description¶
This entity performs multiplication of two fixed-point numbers.
Latency of this entity is OpRegs_g clock cycles plus optional rounding and saturation registers. The default generics lead to a latency of 3 clock cycles.
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| AFmt_g | string | - | Input A format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| BFmt_g | string | - | Input B format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| ResultFmt_g | string | - | Format of the result String representation of an en_cl_fix Format_t (e.g. "(0,1,15)") |
| Round_g | string | "Trunc_s" | Rounding mode String representation of an en_cl_fix FixRound_t. |
| Saturate_g | string | "Warn_s" | Saturation mode String representation of an en_cl_fix FixSaturate_t. |
| OpRegs_g | natural | 1 | Number of pipeline stages for the operation |
| RoundReg_g | string | "YES" | Presence of rounding pipeline stage "YES": Always implement register "NO": Never implement register "AUTO": Implement register if rounding is needed according to the formats chosen |
| SatReg_g | string | "YES" | Presence of saturation pipeline stage "YES": Always implement register "NO": Never implement register "AUTO": Implement register if saturation is needed according to the formats chosen |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | '0' | Clock Not required if all registers are disabled (OpRegs_g=0, RoundReg_g="NO", SatReg_g="NO") |
| Rst | in | 1 | '0' | Reset input (high-active, synchronous to Clk) Not required if all registers are disabled (OpRegs_g=0, RoundReg_g="NO", SatReg_g="NO") |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_A | in | width(AFmt_g) | - | Input data Format: AFmt_g |
| In_B | in | width(BFmt_g) | - | Input data Format: BFmt_g |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for In_A and In_B |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Result | out | width(ResultFmt_g) | N/A | Result data Format ResultFmt_g |
| Out_Valid | out | 1 | N/A | AXI-S handshaking signal for Out_Result |
Detail¶
Below figure shows the implementation of olo_fix_mult
