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olo_ft_ecc_encode

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Status Information

VHDL Source: olo_ft_ecc_encode

Description

This entity provides a reusable, optionally pipelined SECDED encoder. It wraps the eccEncode function from olo_ft_pkg_ecc into a standalone entity exposing an AXI4-Stream forward handshake (In_Valid / In_Ready, Out_Valid / Out_Ready).

A codeword-wide error-injection side channel is also provided. The injection pattern is latched on ErrInj_Valid and applied to the next accepted data beat. If ErrInj_Valid is asserted in the same cycle as a completed handshake, the pattern is applied directly without going through the latch. See Open Logic Fault-Tolerance Principles - Error Injection for the latched-injection semantics shared across the ft area.

Use cases:

  • Inside ECC-protected RAM/FIFO entities in the ft area (instantiated by olo_ft_ram_sp and friends to avoid duplicating the encoder body).
  • Forward error correction (FEC) over a transmission link.
  • AXI4-Stream traffic that is buffered in unprotected external memory (encode at the producer, decode at the consumer with olo_ft_ecc_decode).

Pipeline structure

The Pipeline_g generic inserts register stages on the encode datapath. The range is 0..1.

Pipeline_g Structure
0 Combinational eccEncode + injection XOR (no register). Out_Codeword tracks In_Data within the same cycle as a completed handshake.
1 Combinational eccEncode + injection XOR feeds a single register at the output. Breaks the combinational path from upstream logic to whatever consumes Out_Codeword.

Generics

Name Type Default Description
Width_g positive - Number of uncoded data bits
Pipeline_g natural 0 Number of register stages (range 0..1). 0 = combinational output, 1 = register near output.
UseReady_g boolean true If true, In_Ready honours back-pressure from Out_Ready (shadow-register pipeline). If false, In_Ready is hard-wired to '1' and the pipeline is a plain register chain.

Interfaces

Clock and Reset

Name In/Out Length Default Description
Clk in 1 - Clock
Rst in 1 - Reset (high-active, synchronous to Clk). Clears the injection latch and the pipeline valid register(s).

Input

Name In/Out Length Default Description
In_Valid in 1 '1' AXI4-Stream handshaking signal for In_Data
In_Ready out 1 N/A AXI4-Stream handshaking signal for In_Data
In_Data in Width_g - Data word to encode

Output

Name In/Out Length Default Description
Out_Valid out 1 N/A AXI4-Stream handshaking signal for Out_Codeword
Out_Ready in 1 '1' AXI4-Stream handshaking signal for Out_Codeword
Out_Codeword out eccCodewordWidth(Width_g) N/A SECDED-encoded codeword (with any injection applied)

Error Injection

Name In/Out Length Default Description
ErrInj_BitFlip in eccCodewordWidth(Width_g) all 0 Codeword-wide bit-flip pattern. XORed into the encoded codeword before it leaves the entity.
ErrInj_Valid in 1 '0' Strobe that latches ErrInj_BitFlip. The latched pattern is applied to the next accepted data beat, then cleared.