olo_fix_round¶
Status Information¶
VHDL Source: olo_fix_round
Bit-true Model: olo_fix_round
Description¶
This entity allows reducing the number of fractional bits in a fixed-point number and executes rounding.
Note: The output format MUST be one that ONLY requires rounding. It is not allowed to select any other number of integer bits than exactly the one required.
Format examples:
- AFmt_g="(1,2,4)", ResultFmt_g="(1,3,3)", Round_g="NonSymPos_s"
- Requires 3 integer bits because rounding up the highes possible input value requires one more integer bit
- AFmt_g="(1,2,4)", ResultFmt_g="(1,2,3)", Round_g="Trunc_s"
- Does not required an additional integer bit because truncation does never lead to higher output than input
Latency of this entity is given by the optional rounding register. The default generics lead to a latency of 1 clock cycle.
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| AFmt_g | string | - | Input A format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| ResultFmt_g | string | - | Format of the result String representation of an en_cl_fix Format_t (e.g. "(0,1,15)") |
| Round_g | string | "NonSymPos_s" | Rounding mode String representation of an en_cl_fix FixRound_t. |
| FmtCheck_g | boolean | true | If true, an error is thrown in case ResultFmt_g is not as required |
| RoundReg_g | string | "YES" | Presence of rounding pipeline stage "YES": Always implement register "NO": Never implement register "AUTO": Implement register if rounding is needed according to the formats chosen |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | '0' | Clock Not required if all registers are disabled (RoundReg_g="NO") |
| Rst | in | 1 | '0' | Reset input (high-active, synchronous to Clk) Not required if all registers are disabled (RoundReg_g="NO") |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_A | in | width(AFmt_g) | - | Input data Format: AFmt_g |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for In_A |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Result | out | width(ResultFmt_g) | N/A | Result data Format ResultFmt_g |
| Out_Valid | out | 1 | N/A | AXI-S handshaking signal for Out_Result |
Detail¶
No detailed description required. All details that could be mentioned here are already covered by fixed point principles.