olo_ft_fifo_packet¶
Status Information¶
VHDL Source: olo_ft_fifo_packet
Description¶
This component implements an ECC-protected synchronous packet FIFO using SECDED (Single Error Correction, Double Error Detection) Hamming code. The interface and behavior (store and forward, packet drop on the write side, packet skip/repeat on the read side) match olo_base_fifo_packet.
The ECC is transparent to the user: data is automatically encoded on write and decoded/corrected on read. Error status flags indicate whether a single-bit error was corrected or a double-bit error was detected.
In contrast to the base entity, FeatureSet_g = "DROP_ONLY" is not supported and rejected at
elaboration: in that mode the packet-framing In_Last flag would be stored inside the main RAM where it is
not covered by the ECC parity (see
Fault-Tolerant Storage of Packet Boundaries).
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| Width_g | positive | - | Number of data bits per FIFO entry. The internal FIFO is wider to accommodate ECC parity bits. |
| Depth_g | positive | - | Number of entries (must be a power of two) |
| FeatureSet_g | string | "FULL" | "FULL" or "DROP_SKIP_ONLY". "DROP_ONLY" is not supported and rejected at elaboration (see Fault-Tolerant Storage of Packet Boundaries). |
| RamStyle_g | string | "auto" | Controls the RAM implementation resource |
| RamBehavior_g | string | "RBW" | Controls the RAM behavior. "RBW" or "WBR" |
| SmallRamStyle_g | string | "registers" | RAM style for the internal packet-boundary FIFO. The default "registers" keeps the packet boundaries in flip-flops so they can be covered by vendor TMR (see Fault-Tolerant Storage of Packet Boundaries). Overriding this to a RAM primitive re-introduces non-ECC-protected RAM state and is discouraged for fault-tolerant designs. |
| SmallRamBehavior_g | string | "same" | RAM behavior for the internal packet-boundary FIFO |
| MaxPackets_g | positive | 17 | Maximum number of packets in the FIFO (min 2) |
Interfaces¶
Clock and Reset¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset (high-active, synchronous to Clk). Empties the FIFO and clears the internal error-injection latch. |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_Valid | in | 1 | '1' | Input valid (AXI-S handshaking) |
| In_Ready | out | 1 | N/A | Input ready (AXI-S handshaking) |
| In_Data | in | Width_g | - | Input data |
| In_Last | in | 1 | '1' | End of packet |
| In_Drop | in | 1 | '0' | Drop the packet currently being written |
| In_IsDropped | out | 1 | N/A | Indicates the current input packet is being dropped |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Valid | out | 1 | N/A | Output valid (AXI-S handshaking) |
| Out_Ready | in | 1 | '1' | Output ready (AXI-S handshaking) |
| Out_Data | out | Width_g | N/A | Output data (corrected if a single-bit error was detected) |
| Out_Size | out | ceil(log2(Depth_g+1)) | N/A | Packet size in words |
| Out_Last | out | 1 | N/A | End of packet |
| Out_Next | in | 1 | '0' | Skip to the next packet. Acts on the beat observed at the output, as in the base FIFO. |
| Out_Repeat | in | 1 | '0' | Repeat the current packet (FULL feature set only). Acts on the beat observed at the output, as in the base FIFO. |
| Out_EccSec | out | 1 | N/A | Single error corrected flag. Time-aligned with Out_Data. |
| Out_EccDed | out | 1 | N/A | Double error detected flag. Read data is unreliable. Time-aligned with Out_Data. |
Status¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| PacketLevel | out | ceil(log2(MaxPackets_g+1)) | N/A | Number of complete packets in FIFO |
| FreeWords | out | ceil(log2(Depth_g+1)) | N/A | Number of free word slots |
Error Injection (optional)¶
These ports drive the internal olo_ft_ecc_encode instance. Leave them unconnected for normal operation; see Open Logic Fault-Tolerance Principles - Error Injection for the latched-strobe semantics shared across the ft area.
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_ErrInj_BitFlip | in | eccCodewordWidth(Width_g) | all 0 | Codeword-wide flip pattern. Each '1' bit XORs (flips) the corresponding bit of the stored codeword. Popcount 1 = SEC-correctable, popcount 2 = DED-detectable. |
| In_ErrInj_Valid | in | 1 | '0' | Strobe that latches In_ErrInj_BitFlip into the encoder's pending-injection register. The latched pattern is applied to the next accepted input beat. |
Detailed Description¶
Architecture¶
The entity is composed of three Open Logic entities:
- olo_ft_ecc_encode encodes each accepted input beat into a SECDED codeword.
- olo_base_fifo_packet stores the codeword (entity configured with a codeword-wide word). In_Last, In_Drop, Out_Next, Out_Repeat, Out_Last, Out_Size and the status outputs connect straight through.
- olo_ft_ecc_decode decodes and corrects each beat on the read side and drives Out_EccSec / Out_EccDed.
The codeword is protected end-to-end while it is inside the FIFO: encoding happens before, and decoding after, all storage elements.
Combinational ECC Encoder and Decoder¶
Both codecs are instantiated with Pipeline_g = 0. The datapath to and from the internal FIFO is
therefore combinational, and the ft entity behaves exactly like its
olo_base_fifo_packet counterpart.
The ECC decode lies between the RAM output and the output ports and is the critical path of the entity. Where it limits the clock frequency, use olo_base_fifo_packet directly and place registered olo_ft_ecc_encode / olo_ft_ecc_decode instances around it in the surrounding design. Out_Last and Out_Size must then be delayed by the same number of stages as the data, and the levels and status flags of the base FIFO do not account for the beats held in the codec pipelines.
Fault-Tolerant Storage of Packet Boundaries¶
The design goal for the ft area is that no RAM-resident state is outside the ECC protection: RAM cells hold their content for arbitrarily long and cannot be covered by vendor TMR, so anything stored in RAM must be part of an ECC codeword. For the packet FIFO this drives two decisions:
FeatureSet_g = "DROP_ONLY"is rejected at elaboration. In that mode the base FIFO widens the main RAM by one bit and stores the In_Last flag of every word alongside the data, because it keeps no per-packet boundary records elsewhere. That bit would sit inside the RAM but outside the ECC codeword: a single upset would silently split or merge packets (no Out_EccDed indication) and could desynchronize the FIFO's packet accounting. In the supported feature sets ("FULL", "DROP_SKIP_ONLY") the main RAM holds pure ECC codewords only.- The packet-boundary FIFO defaults to
SmallRamStyle_g = "registers". In the supported feature sets the packet-end addresses (which drive Out_Last, Out_Size and the Out_Next jump target) are stored in a small internal FIFO. With the "registers" style this storage is implemented in flip-flops, which vendor TMR (syn_radhardlevel = "tmr") covers like all other control logic. Verify in the synthesis report that no RAM primitive is inferred for it on your target tool (on tools where "registers" is not a recognized RAM-style value, e.g. Intel Quartus which uses "logic", override the generic accordingly). Overriding SmallRamStyle_g to a block/distributed RAM saves a few hundred flip-flops but re-introduces non-ECC-protected RAM state and is therefore discouraged for fault-tolerant designs.
ECC Overhead, Error Injection and Status Flags¶
See the corresponding sections in Open Logic Fault-Tolerance Principles:
- ECC Overhead - internal storage width vs. data width
- Error Injection - semantics of In_ErrInj_BitFlip / In_ErrInj_Valid
- Error Status Flags - meaning of Out_EccSec / Out_EccDed
Constraints¶
- The packet-boundary records (packet-end addresses, from which Out_Last and Out_Size are derived) are not part of the ECC codeword. They are kept in flip-flops by default (see Fault-Tolerant Storage of Packet Boundaries) and must be covered by vendor TMR as part of the surrounding radiation-hardened design, like all other control logic.
- See Open Logic Fault-Tolerance Principles - Constraints That Apply Across the Area for the constraints that apply across the ft area.