olo_fix_bin_div¶
Status Information¶
VHDL Source: olo_fix_bin_div
Bit-true Model: olo_fix_bin_div
Description¶
Overview¶
This entity implements a binary division of two fixed-point numbers.
The algorithm can be implemented in two different modes:
- SERIAL
- Iterations are executed one after the other
- A new sample can be accepted every width(OutFmt_g) + 6 clock cycles
- Lowest possible resource usage
- PIPELINED
- Iterations are implemented in individual pipeline stages
- Every clock cycle a new sample can be accepted
- Highest possible throughput
Division by zero returns the highest possible value when Saturate_g = "Sat_s" and an undefined value otherwise.
Latency¶
The latency of the entity depends on several factors and can best be determined in the simulation.
Note: Latency is not guaranteed to be constant across different versions. It's therefore best to design user logic to be independent of the latency of this block (e.g. through olo_base_latency_comp).
In the current version the latency can be calculated as follows:
- Mode_g = "SERIAL": Latency = OutFmt_g.I + OutFmt_g.F + 6
- Mode_g = "PIPELINED": Latency = OutFmt_g.I + OutFmt_g.F + 6
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| NumFmt_g | string | - | Numerator format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| DenomFmt_g | string | - | Denominator format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| OutFmt_g | string | - | Output data format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| Mode_g | string | "PIPELINED" | Mode of Operation "SERIAL": one iteration per clock cycle "PIPELINED": Pipelined mode (one sample per clock cycle) |
| Round_g | string | "Trunc_s" | Rounding mode String representation of an en_cl_fix FixRound_t. |
| Saturate_g | string | "Sat_s" | Saturation mode String representation of an en_cl_fix FixSaturate_t. |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_Num | in | width(NumFmt_g) | N/A | Input numerator Format NumFmt_g |
| In_Denom | in | width(DenomFmt_g) | N/A | Input denominator Format DenomFmt_g |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for In_xxx |
| In_Ready | out | 1 | N/A | AXI4-Stream handshaking signal for In_xxx |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Quot | out | width(OutFmt_g) | - | Quotient output data Format: OutFmt_g |
| Out_Valid | out | 1 | N/A | AXI4-Stream handshaking signal for Out_Quot |
Note The output interface does not implement backpressure (Ready). If backpressure is required, the user ideally implements it over the whole processing chain using olo_base_flowctrl_handler.
Detail¶
The entity converts numerator and denominator to unsigned numbers, so the division can be implemented using a simple non-restoring division algorithm. At the output the sign is then restored correctly.
