This entity provides a reusable, optionally pipelined SECDED decoder. It wraps the package functions
eccSyndromeAndParity,
eccCorrectData,
eccSecError and eccDedError into a single
standalone entity exposing an AXI4-Stream handshake (In_Valid / In_Ready, Out_Valid / Out_Ready).
Single-bit errors (SEC) are corrected before Out_Data is driven. Double-bit errors (DED) are detected via
Out_EccDed but cannot be corrected. Out_Data, Out_EccSec and Out_EccDed are time-aligned.
A codeword-wide error-injection side channel is also provided. The injection pattern is latched on
ErrInj_Valid and XORed into the codeword on the next accepted beat (simulating an in-transit
corruption — useful for FEC scenarios). See
Open Logic Fault-Tolerance Principles - Error Injection for the
latched-injection semantics shared across the ft area.
The Pipeline_g generic inserts register stages on the decode datapath. The range is 0..2 and
the pipeline is explicitly distributed across the SECDED stages rather than relying on
register-retiming:
Pipeline_g
Structure
0
Combinational decode (no register).
1
Combinational syndrome + correction + SEC/DED → register near the output. Breaks the path from the decoder to downstream logic.
2
Combinational syndrome → register {InjectedCw, SynPar} → combinational correction + SEC/DED → register {Out_Data, Out_EccSec, Out_EccDed}. Breaks both the syndrome path and the correction path - use this when both halves of the SECDED logic need their own clock cycle to close timing.
Number of register stages (range 0..2). See Pipeline structure above.
UseReady_g
boolean
true
If true, In_Ready honours back-pressure from Out_Ready (shadow-register pipeline). If false, In_Ready is hard-wired to '1' and the pipeline is a plain register chain.