Skip to content

Back to Readme

Entity List

Note that components are split into categories.

Table of Contents

base

This area contains all base functionality that is required in most FPGA designs.

Packages (olo_base_pkg_\<...>)

Packages with type declarations and functions used in Open Logic internally or on its interfaces.

Package Description
olo_base_pkg_array Array type definitions (e.g. arrays of std_logic_vector)
olo_base_pkg_math Mathematic functions (e.g. log2)
olo_base_pkg_logic Mathematic functions (e.g. binaryToGray)
olo_base_pkg_string String functions (e.g. toLower)
olo_base_pkg_crc Crc Settings definitions (e.g. Crc8_DvbS2_c)
olo_base_pkg_attribute Definition of synthesis attributes for different tools. For internal use within Open Logic only

Clock Crossings (olo_base_cc\<...>_)

Clock crossings are a key topic and they all follow the same clock crossing principles.

A selection table summarizing the pros and cons of all the different clock crossings is also provided in clock crossing principles. If unsure which entity to select, refer to this table.

Entity Description
olo_base_cc_reset Synchronization of resets between two clock domains (bi-directional)
olo_base_cc_bits Transfer a group of individual single bit signals from one clock domain to another clock domain
olo_base_cc_pulse Transfer single-cycle pulses from one clock domain to another clock domain
olo_base_cc_simple Transfer selectively valid data from one clock domain to another clock domain (data/valid pair)
olo_base_cc_status Transfer status and configuration information from one clock domain to another clock domain. The update rate is relatively low but consistency is guaranteed
olo_base_cc_n2xn Transfer data from a slower clock to a faster phase aligned clock (output clock frequency is an exact integer multiple of the input clock frequency and the clocks are phase aligned).
olo_base_cc_xn2n Transfer data from a faster clock to a slower phase aligned clock (input clock frequency is an exact integer multiple of the output clock frequency and the clocks are phase aligned).
olo_base_cc_handshake Transfer data from one clock domain to another clock domain using the standard Valid/Ready handshaking.
For technologies with distributed RAM (LUT can be used as small RAM), olo_base_fifo_async in most cases is preferred over this entity.
olo_base_fifo_async Asynchronous FIFO (separate write and read clocks)
This is not a pure clock-crossing entity but it can be used as such.

RAM Implementations (olo_base_ram_\<...>)

Entity Description
olo_base_ram_sp Single port RAM
olo_base_ram_sdp Simple dual-port RAM
olo_base_ram_tdp True dual-port RAM

FIFO Implementations (olo_base_fifo_\<...>)

Entity Description
olo_base_fifo_sync Synchronous FIFO (single clock)
olo_base_fifo_async Asynchronous FIFO (separate write and read clocks)
olo_base_fifo_packet Packet FIFO (store and forward) with the ability to drop packets on the write side and skip or repeat packets on the read side

Width Conversions (olo_base_wconv_\<...>)

Entity Description
olo_base_wconv_n2xn Increase word width by an integer factor (OutWidth = InWidth x N)
Convert from TDM to parallel (see Conventions)
olo_base_wconv_xn2n Decrease word width by an integer factor (OutWidth = InWidth / N)
Convert from parallel to TDM (see Conventions)
olo_base_wconv_n2m Arbitrary word width converter

Arbiters (olo_base_arb_\<...>)

Entity Description
olo_base_arb_prio Priority arbiter - Always selects the highest priority requester with a pending request.
olo_base_arb_rr Round robin arbiter - iterate through all requesters with a pending request.
olo_base_arb_wrr Weighted Round robin arbiter - iterate through all requesters based on assigned weights with a pending request.

TDM (olo_base_tdm_\<...>)

See Conventions for a description about TDM (time-division-multiplexing).

Entity Description
olo_base_tdm_mux Select one specific channel from a TDM signal.
olo_base_wconv_n2xn Convert from TDM to parallel (see Conventions)
This is not a pure TDM entity but it can be used for TDM purposes.
olo_base_wconv_xn2n Convert from parallel to TDM (see Conventions)
This is not a pure TDM entity but it can be used for TDM purposes.
Entity Description
olo_base_delay Fixed duration delay (fixed number of data-beats)
olo_base_delay_cfg Configurable duration delay (runtime configurable number of data-beats)
olo_base_strobe_gen Strobe generator. Generate pulses at a fixed frequency
olo_base_strobe_div Strobe divider. Only forward every N'th pulse (divide event frequency).
Can also be used to convert single-cycle pulses to acknowledged events (pulse stays active until acknowledged).
olo_base_rate_limit Rate limiter for AXI4-Stream interfaces - limits the data rate to a specified maximum value.
olo_base_latency_comp Latency compensator for AXI4-Stream interfaces - delays data bypassing a processing element to compensate for the latency

Miscellaneous

Entity Description
olo_base_pl_stage Implements one or more pipeline stages (register stages) - with or without support for backpressure (Ready)
olo_base_dyn_sft Dynamic barrel shifter (number of bits to shift is configurable per sample at runtime)
olo_base_prbs PRBS (pseudo random binary sequence) generator based on linear feedback shift register (LFSR) implementation.
olo_base_reset_gen Reset generator - Generates reset pulses of specified duration after configuration and upon request
olo_base_cam Content addressable memory
olo_base_flowctrl_handler Implements full flow-control (including Ready/back-pressure) around processing entities that do not support Ready/back-pressure natively.
olo_base_decode_firstbit Implements a first-bit decoder (finds the index of the first bit set in a vector). Allows pipelining for operating on very wide vectors at high clock frequencies.
olo_base_crc CRC calculation engine
olo_base_crc_append Append CRC to AXI4-Stream packets
olo_base_crc_check Check CRC of AXI4-Stream packets and drop invalid packets
olo_base_sample_hold Sample and hold for bit-vectors. Holds the last sampled value until a new sample is taken.

axi

This area contains AXI4 related elements.

Entity Description
olo_axi_pl_stage Implements a AXI4 pipeline stage, registering all signals of an AXI4 interface.
Can be used for AXI4-Lite as well.
olo_axi_lite_slave Interface to attach user register banks and memories to the AXI4-Lite bus.
olo_axi_master_simple AXI4 master - does execute arbitrarily sized transfer over AXI4. The __simple_ version of the master does only allow access to word-aligned addresses and sizes.
olo_axi_master_full AXI4 master - Same as olo_axi_master_simple but does allow access that are not word-aligned (in terms of start address, size or both).

Note: Open Logic focuses on providing utilities for development of AXI endpoints (masters and slaves). Open Logic does not aim to provide AXI interconnect infrastructure (e.g. crossbars, interconnects, ...). Often the vendor IPs are used (for tool integration reasons) for these aspects. If you are looking for a pure VHDL implementation of AXI interconnects, it's suggested that you use one of the following libraries:

  • hdl-modules
    • hdl-modules utilizes VHDL-2008 which has limited support in some tools (namely the Standard and Lite versions of Quartus Prime)
    • hdl-modules currently does only contain synthesis attributes for AMD (Vivado)
  • SURF
    • SURF currently does only target AMD (Vivado) and Altera (Quartus Prime)

intf

This area contains components related to interfacing to external components.

Entity Description
olo_intf_sync Double stage synchronizer for external signals.
olo_intf_i2c_master I2C Master - Supports the full standard including arbitration (multi-master I2C) and clock stretching.
olo_intf_spi_master SPI Master - Supports handling multiple slaves and variable width transactions as well as all clock phases and poloarities and LSB/MSB first.
olo_intf_spi_slave SPI Slave - Supports all clock phases and poloarities and LSB/MSB first.
olo_intf_uart UART
olo_intf_debounce Debouncer (for bouncing signals from buttons and switches) - Includes double-stage synchronizers.
olo_intf_clk_meas Measure the frequency of a clock.

fix

This area contains fixed point mathematic related functionality.

All fixed point mathematics functions in Open Logic follow a common cent of principles described in Open Logic Fixed-Point Principles. Read through this document before using the components.

Packages

Below packages contain basic definitions like number format types etc.

Entity Description
en_cl_fix_pkg 3rd Party Package for fixed-point mathematics.
Original source Enclustra GitHub
olo_fix_pkg Package with various Open Logic specific definitions (e.g. common options of string-type generics)

Testbench Utilities

Entity Description
olo_fix_sim_stimuli Read co-simulation file generated by Python and apply its content to the DUT in a HDL simulation.
olo_fix_sim_checker Read co-simulation file generated by Python and check outputs of the DUT in a HDL simulation against it.

Design Utilities

Python File Description
olo_fix_lin_approx Bit-true model and code generator for linear function approximations (see olo_fix_lin_approx_calc).
olo_fix_pkg_writer Generate HDL (VHDL or Verilog) package with all number formats defined in Python.
olo_fix_cosim Python utilities for co-simulation with HDL simulators. Generate co-simulation files that can be read by olo_fix_sim_stimuli and olo_fix_sim_checker in HDL simulations.

Basic Operations

Entity Description
olo_fix_round Rounding to a number format with less fractional bits.
Instead of this component, the cl_fix_round() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_saturate Saturate to a number format with less integer bits
Instead of this component, the cl_fix_saturate() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_resize Resize to a different number format.
Instead of this component, the cl_fix_resize() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_from_real Convert real number to fixed-point representation - for synthesis.
Instead of this component, the cl_fix_from_real() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_sim_from_real Convert real number to fixed-point representation - for simulations.
Instead of this component, the cl_fix_from_real() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_to_real Convert fixed-point number to real representation.
Instead of this component, the cl_fix_to_real() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_add Add two fixed point numbers.
Instead of this component, the cl_fix_add() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_sub Subtract two fixed point numbers.
Instead of this component, the cl_fix_sub() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_addsub Selectively add or subtract two fixed point numbers.
Instead of this component, the cl_fix_addsub() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_mult Multiply two fixed point numbers.
Instead of this component, the cl_fix_mult() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_neg Negate a fixed point number.
Instead of this component, the cl_fix_neg() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_abs Get the absolute value of a fixed point number.
Instead of this component, the cl_fix_abs() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)
olo_fix_compare Compare two fixed point numbers.
Instead of this component, the cl_fix_compare() function from en_cl_fix_pkg can be used alternatively (for usage from VHDL)

Note: For basic fixed point functionality either components from Open Logic of functions from en_cl_fix_pkg can be used. For deciding which option to use, the following considerations shall be taken into account:

  • Functions cannot be called from Verilog - hence Open Logic components are the only option for Verilog
  • Open Logic components include pipeline register stages - for fast clock speeds, this can lead to more readable code
  • en_cl_fix_pkg functions allow packing several steps into one process, which can lead to more compact code

Simple Mathematics

Entity Description
olo_fix_limit Limit a value between an upper and a lower bound
olo_fix_bin_div Binary division of two fixed point numbers
olo_fix_cplx_addsub Add or Subtract two complex fixed point numbers.
olo_fix_cplx_mult Multiply two complex fixed point numbers.
Supports a mixer mode (complex-to-complex)
olo_fix_madd Multiply-accumulate (MAC) operation on fixed point numbers.
Aimed to be used to build MACC chains (e.g. for FIR filters)

Mixers

Entity Description
olo_fix_cplx_mult Can be used as complex-to-complex mixer in MIX mode
olo_fix_mix_r2c Real to complex mixer. Mixes a real signal with a complex local oscillator
olo_fix_mix_c2r Complex to real mixer. Mixes a complex signal with a complex local oscillator to produce a real output

CORDIC

Entity Description
olo_fix_cordic_vect CORDIC vectoring mode - cartesian to polar conversion
olo_fix_cordic_rot CORDIC rotating mode - polar to cartesian conversion

CIC Filters

Entity Description
olo_fix_cic_dec_tdm CIC decimator (TDM input, TDM output), single- or multi-channel, ratio fixed or runtime configurable
olo_fix_cic_dec_par_tdm CIC decimator (parallel input, TDM output), single- or multi-channel, ratio fixed or runtime configurable

FIR Filters

Naming convention: olo_fix_fir_<dec/int>_\<ser/par/semi>_ch\<tdm/par>

  • dec/int: decimating or interpolating FIR filter
  • ser/par/semi: Tap processing (serial, parallel or semi-parallel)
  • tdm/par: TDM or parallel channel handling on input and output
Entity Description
olo_fix_fir_dec_ser_chtdm Decimating FIR filter (TDM channels, serial tap computation), multi-channel only (not usable for single-channel)
Runtime-configurable or fixed ratio, tap count and coefficients - Can be used non-decimating (Ratio = 1)
olo_fix_fir_dec_ser_chpar Decimating FIR filter (parallel channels, serial tap computation), single- or multi-channel (one multiplier per channel)
Runtime-configurable or fixed ratio, tap count and coefficients - Can be used non-decimating (Ratio = 1)
olo_fix_fir_dec_semi_chtdm Decimating FIR filter (TDM channels, semi-parallel tap computation with a configurable number of chained multipliers), single- or multi-channel
Fixed ratio and tap count, fixed or runtime-configurable coefficients - Can be used non-decimating (Ratio = 1)

Function Approximations

Entity Description
olo_fix_lin_approx_calc Linear approximation of an arbitrary function (table based). Tables and wrapper entities are generated by olo_fix_lin_approx.
olo_fix_cordic_rot CORDIC rotating mode - Can be used to approximate sine/cosine functions
olo_fix_sin Sine and (optionally) cosine of a phase given in rotations. Based on piecewise linear approximation.
olo_fix_inv Inversion (1/x) of a fixed point number. Based on shifting and piecewise linear approximation.
olo_fix_sqrt Square root of a fixed point number. Based on shifting and piecewise linear approximation.

Miscellaneous

Entity Description
olo_fix_coef_storage Fixed-point coefficient storage - ROM or RAM with Coef read port and optional Cfg write/readback port.
olo_fix_sample_hold Sample and hold a fixed point number - output holds the last sampled value until a new sample is taken.
olo_fix_mov_avg Moving average filter
olo_fix_lin_approx_calc Linear approximation of an arbitrary function (table based). Tables and wrapper entities are generated by olo_fix_lin_approx.

ft

This area contains fault-tolerant entities for use in radiation-sensitive environments (e.g. space or avionics). All RAM entities use SECDED (Single Error Correction, Double Error Detection).

The cross-cutting concepts (codeword layout, ECC overhead, error injection semantics, status flags, ECC pipeline, common constraints) are described once in Open Logic Fault-Tolerance Principles and referenced from the per-entity docs.

Packages (olo_ft_pkg_\<...>)

Package Description
olo_ft_pkg_ecc SECDED Hamming code functions for ECC-protected memories.
olo_ft_pkg_attribute Synthesis attributes specific to fault-tolerant (TMR) designs. For internal use within Open Logic only

ECC Codec (olo_ft_ecc_\<...>)

Entity Description
olo_ft_ecc_encode SECDED encoder with AXI4-Stream handshake, optional pipeline, and codeword-wide bit-flip injection
olo_ft_ecc_decode SECDED decoder with AXI4-Stream handshake and optional distributed pipeline

Clock Crossings (olo_ft_cc_\<...>)

TMR-hardened counterparts of the olo_base_cc_\<...> clock crossings. Each chain is triplicated with a majority voter to mitigate single-event upsets. They follow the same clock crossing principles as their base counterparts.

Entity Description
olo_ft_cc_reset TMR-hardened synchronization of resets between two clock domains (bi-directional)
olo_ft_cc_bits TMR-hardened transfer of a group of individual single bit signals from one clock domain to another clock domain
olo_ft_cc_pulse TMR-hardened transfer of single-cycle pulses from one clock domain to another clock domain
olo_ft_cc_simple TMR-hardened transfer of selectively valid data from one clock domain to another clock domain (data/valid pair)
olo_ft_cc_status TMR-hardened transfer of status and configuration information from one clock domain to another clock domain. The update rate is relatively low but consistency is guaranteed
olo_ft_cc_handshake TMR-hardened transfer of data from one clock domain to another clock domain using the standard Valid/Ready handshaking.
For high data rates, olo_ft_fifo_async is preferred over this entity.

Resets and Synchronizers (ft)

TMR-hardened counterparts of olo_base_reset_gen and olo_intf_sync.

Entity Description
olo_ft_reset_gen TMR-hardened reset generator - Generates reset pulses of specified duration after configuration and upon request
olo_ft_sync TMR-hardened synchronizer for asynchronous input signals

RAM Implementations (olo_ft_ram_\<...>)

The ECC-protected counterparts of the olo_base_ram_\<...> entities. The scrub variants additionally repair single-bit errors in the background and have no base counterpart.

Entity Description
olo_ft_ram_sp ECC-protected single port RAM
olo_ft_ram_sp_scrub ECC-protected single-port RAM with an opportunistic background memory scrubber
olo_ft_ram_sdp ECC-protected simple dual port RAM
olo_ft_ram_sdp_scrub ECC-protected simple dual-port RAM with an opportunistic background memory scrubber
olo_ft_ram_tdp ECC-protected true dual-port RAM

FIFO Implementations (olo_ft_fifo_\<...>)

The ECC-protected counterparts of the olo_base_fifo_\<...> entities.

Entity Description
olo_ft_fifo_sync ECC-protected synchronous FIFO (single clock)
olo_ft_fifo_async ECC-protected asynchronous FIFO (separate write and read clocks)
olo_ft_fifo_packet ECC-protected packet FIFO (store and forward) with the ability to drop packets on the write side and skip or repeat packets on the read side
Entity Description
olo_ft_delay ECC-protected fixed duration delay (fixed number of data-beats)
olo_ft_delay_cfg ECC-protected configurable duration delay (runtime configurable number of data-beats)

AXI Interfaces (olo_ft_axi_\<...>)

Entity Description
olo_ft_axi_master_simple ECC-protected AXI4 master (simple interface, aligned transfers)
olo_ft_axi_master_full ECC-protected AXI4 master with unaligned-access support and width conversion

Monitoring (olo_ft_ecc_monitor\<...>)

Entity Description
olo_ft_ecc_monitor EDAC monitor: per-channel saturating SEC/DED counters with sticky DED flags and a read-and-clear port
olo_ft_ecc_monitor_axi EDAC monitor with AXI4-Lite register interface and interrupt output

Private Entities

Internal building blocks instantiated by other ft entities. They are documented for reference but not intended for direct end-user instantiation.

Entity Description
olo_ft_private_scrubber Opportunistic memory-scrub engine (FSM and user/scrub arbitration) shared by the two scrub RAM wrappers
olo_ft_private_cc_toggle TMR-hardened toggle-based pulse crossing without reset crossing, shared by the olo_ft_cc_simple/status/handshake clock crossings