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olo_ft_delay

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Status Information

VHDL Source: olo_ft_delay

Description

This component implements an ECC-protected fixed-duration delay using SECDED (Single Error Correction, Double Error Detection) Hamming code. The interface and behavior match olo_base_delay: the input data is delayed by a fixed number of data-beats (In_Valid = '1' cycles).

The ECC is transparent to the user: data is automatically encoded at the input and decoded/corrected at the output. Error status flags indicate whether a single-bit error was corrected or a double-bit error was detected.

Generics

Name Type Default Description
Width_g positive - Number of data bits. The internal delay line is wider to accommodate ECC parity bits.
Delay_g natural - Delay in data-beats (In_Valid = '1' cycles). Delay of 0 implements a combinational feed-through.
Resource_g string "AUTO" "AUTO", "SRL" or "BRAM". See olo_base_delay and the note on storage protection below.
BramThreshold_g positive 128 In "AUTO" mode, BRAM is used for delays >= BramThreshold_g. Applies to the internal (wrapped) delay, which is one beat shorter when EccPipeline_g = 1.
RstState_g boolean true true: the first Delay_g output beats after reset read as zero (with clean error flags). false: the content of the delay-line storage after reset is undefined, including the error flags.
RamBehavior_g string "RBW" Controls the RAM behavior. "RBW" or "WBR"
RamStyle_g string "auto" Controls the RAM implementation resource
EccPipeline_g natural 0 0: combinational ECC decode at the output. 1: one In_Valid-gated register on the decoded outputs; the wrapped delay is shortened by one beat internally, so the total delay stays exactly Delay_g. Requires Delay_g >= 1.

Interfaces

Clock and Reset

Name In/Out Length Default Description
Clk in 1 - Clock
Rst in 1 - Reset (high-active, synchronous to Clk). Restarts the RstState_g warm-up and clears the internal error-injection latch. The delay-line storage content is unaffected but masked by the warm-up.

Data

Name In/Out Length Default Description
In_Data in Width_g - Input data
In_Valid in 1 '1' Data-beat strobe. The delay line only advances on In_Valid = '1' cycles; outputs hold their value in between.
Out_Data out Width_g N/A Delayed output data (corrected if a single-bit error was detected)
Out_EccSec out 1 N/A Single error corrected flag. Time-aligned with Out_Data.
Out_EccDed out 1 N/A Double error detected flag. Output data is unreliable. Time-aligned with Out_Data.

Error Injection (optional)

These ports drive the internal olo_ft_ecc_encode instance. Leave them unconnected for normal operation; see Open Logic Fault-Tolerance Principles - Error Injection for the latched-strobe semantics shared across the ft area.

Name In/Out Length Default Description
In_ErrInj_BitFlip in eccCodewordWidth(Width_g) all 0 Codeword-wide flip pattern. Each '1' bit XORs (flips) the corresponding bit of the stored codeword. Popcount 1 = SEC-correctable, popcount 2 = DED-detectable.
In_ErrInj_Valid in 1 '0' Strobe that latches In_ErrInj_BitFlip into the encoder's pending-injection register. The latched pattern is applied to the next In_Valid beat.

Detailed Description

Architecture

The entity is a sandwich of three Open Logic entities:

  1. olo_ft_ecc_encode encodes each In_Valid beat into a SECDED codeword (combinational).
  2. olo_base_delay delays the codeword (entity configured with a codeword-wide word).
  3. olo_ft_ecc_decode decodes and corrects the delayed codeword and drives Out_EccSec / Out_EccDed time-aligned with Out_Data.

With EccPipeline_g = 1, one additional In_Valid-gated register is placed on the decoded outputs and the wrapped delay runs one beat shorter, so the total delay stays exactly Delay_g and the outputs are driven from a fabric register (restoring the registered-output property of the base entity).

Storage-Medium Independent Protection

Because encoding happens before, and decoding after, all storage elements, every storage tap holds a full ECC codeword: the SRL cells (LUT-based shift registers or MLABs), the BRAM content and the base entity's output register alike. A single upset in any of these media is corrected at decode and reported on Out_EccSec. Resource_g is therefore a pure resource/timing trade-off with no impact on the protection, which notably makes this entity also the fault-tolerant answer for short delays: LUT-SRL and MLAB cells are dynamic storage that vendor TMR does not cover, so even Resource_g = "SRL" configurations benefit from the ECC.

The address counters and the warm-up counter are regular flip-flops and should be covered by vendor TMR (syn_radhardlevel = "tmr") as part of the surrounding radiation-hardened design, like all other control logic.

ECC Overhead, Error Injection and Status Flags

See the corresponding sections in Open Logic Fault-Tolerance Principles:

Constraints