olo_fix_madd¶
Status Information¶
VHDL Source: olo_fix_madd
Bit-true Model: N/A - used as base for other entities, no direct bit-true model available
Description¶
The entity is not intended for standalone use but serves as base for other entities like FIR filters. Nevertheless, the entity is documented and provided to the user, so that it can be used as a building block for custom entities.
The olo_fix_madd entity performs a multiply-add operation with optional pre-adder. This is a construct that is supported by many FPGAs as a hard-wired DSP block and hence it can be implemented very efficiently.
Note that the entity does not support any rounding or saturation at the output because most hard-wired DSP blocks do not support this or at least not in a consistent and inferrable way. Where not all bits of the result can be represented, truncation is applied.
Inputs InA and InC (if used) are intended to be dynamic signals. InB is intended to be either a dynamic signal as well or a static coefficient that is stored inside a DSP block register (InBIsCoef_g=true).
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Pre-Adder Enabled¶
When the generic PreAdd_g is set to true, the entity performs the following operation:
Latency of this entity is MultRegs_g+3 clock cycles for PreAdd_g=true.
Pre-Adder Disabled¶
When the generic PreAdd_g is set to false, the entity performs the following operation:
Note that in this case, InC_Data is not used and can be left unconnected.
Latency of this entity is MultRegs_g+2 clock cycles for PreAdd_g=false.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| PreAdd_g | boolean | false | Presence of pre-adder stage |
| Operation_g | string | "Add" | Operation to perform in the adder chain "Add": Out = MaccIn + Mult "Sub": Out = MaccIn - Mult |
| PreAddOp_g | string | "Add" | Operation to perform in the pre-adder stage (only used for PreAdd_g=true) "Add": PreAddOut = InA + InC "Sub": PreAddOut = InA - InC |
| AFmt_g | string | - | Input A format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| BFmt_g | string | - | Input B format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| CFmt_g | string | "(0,0,0)" | Input C format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") Ignored for PreAdd_g=false |
| AddChainFmt_g | string | - | Format of the result and MaccIn String representation of an en_cl_fix Format_t (e.g. "(0,1,15)") |
| MultRegs_g | natural | 1 | Number of pipeline stages for the multiplication |
| InBIsCoef_g | boolean | false | Whether InB is a static coefficient that should be stored in a DSP block register (true) or a dynamic signal (false) |
When choosing number formats, keep in mind that in case PreAdd_g=true, the pre-adder multiplier input has one bit more than AFmt_g and CFmt_g to avoid overflow in the pre-adder stage. This is an important consideration for mapping the logic optimally to hard-wired DSP blocks.
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| InA_Data | in | width(AFmt_g) | - | Input data A Format: AFmt_g |
| InC_Data | in | width(CFmt_g) | 0 | Input data C (only used for PreAdd_g=true) Format: CFmt_g |
| InAC_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for InA and InC |
| InB_Data | in | width(BFmt_g) | - | Input data B Format: BFmt_g |
| InB_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for InB |
Adder Chain Input¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| MaccIn | in | width(AddChainFmt_g) | 0 | Input for the adder chain Format: AddChainFmt_g |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Data | out | width(AddChainFmt_g) | N/A | Result data Format: AddChainFmt_g Can be connected to MaccIn of the next stage |
| Out_Valid | out | 1 | N/A | AXI4-Stream handshaking signal for Out_Data |
Detail¶
Valid Handling¶
Out_Valid is asserted when the result of any change of an input indicated by InAC_Valid or InB_Valid is available at the output.
For InBIsCoef_g=true, Out_Valid is only asserted after InAC_Valid was asserted. Reasoning is that no output sample shall be produced when only the coefficient is changed (InB_Valid='1') but only when the data changes (InAC_Valid='1').
