olo_fix_limit¶

Status Information¶

VHDL Source: olo_fix_limit
Bit-true Model: olo_fix_limit

Description¶

This entity limits a signal to a specified range. The range can be given through generics (at compile-time) or through ports (at runtime).

Latency of this entity is two clock cycles plus optional rounding and saturation registers. The default generics lead to a latency of 4 clock cycles.

For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.

Generics¶

Name	Type	Default	Description
InFmt_g	string	-	Data input format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)")
LimLoFmt_g	string	"(1,1,1)"	Lower limit format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") Default given only for the user not having to assign the generic if UseFixedLimits_g=true
LimHiFmt_g	string	"(1,1,1)"	Upper limit format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") Default given only for the user not having to assign the generic if UseFixedLimits_g=true
ResultFmt_g	string	-	Format of the result String representation of an en_cl_fix Format_t (e.g. "(0,1,15)")
Round_g	string	"Trunc_s"	Rounding mode String representation of an en_cl_fix FixRound_t.
Saturate_g	string	"Warn_s"	Saturation mode String representation of an en_cl_fix FixSaturate_t.
UseFixedLimits_g	boolean	false	true: Use FixedLimLo_g and FixedLimHi_g as limits. false: Use ports In_LimLo and In_LimHi as limits.
FixedLimLo_g	real	0.0	Compile time set lower limit (only used if UseFixedLimits_g=true)
FixedLimHi_g	real	0.0	Compile time set upper limit (only used if UseFixedLimits_g=true)
RoundReg_g	string	"YES"	Presence of rounding pipeline stage "YES": Always implement register "NO": Never implement register "AUTO": Implement register if rounding is needed according to the formats chosen
SatReg_g	string	"YES"	Presence of saturation pipeline stage "YES": Always implement register "NO": Never implement register "AUTO": Implement register if saturation is needed according to the formats chosen

Interfaces¶

Control¶

Name	In/Out	Length	Default	Description
Clk	in	1	-	Clock
Rst	in	1	-	Reset input (high-active, synchronous to Clk)

Input Data¶

Name	In/Out	Length	Default	Description
In_Data	in	width(InFmt_g)	-	Input data Format: InFmt_g
In_LimLo	in	width(LimLoFmt_g)	0	Input lower limit Only used if UseFixedLimits_g=false Format: LimLoFmt_g
In_LimHi	in	width(LimHiFmt_g)	0	Input upper limit Only used if UseFixedLimits_g=false Format: LimHiFmt_g
In_Valid	in	1	'1'	AXI4-Stream handshaking signal for In_A and In_B

Output Data¶

Name	In/Out	Length	Default	Description
Out_Result	out	width(ResultFmt_g)	N/A	Result data Format ResultFmt_g
Out_Valid	out	1	N/A	AXI-S handshaking signal for Out_Result

Detail¶

Below figure shows the implementation of olo_fix_limit

First, all inputs are extended to the maximum common format that allows fully representing them all. Then the data is compared to the limits and based on the result either one of the limits or the data is selected. And at the very output the result is resized to ResultFmt_g.

From the structure it is obvious that rounding and saturation are not required if InFmt_g, LimLoFmt_g, LimHiFmt_g and ResultFmt_g are all the same.

Because the logic does never increase the range of the signal, saturation may only be required because of rounding in case of LimLoFmt_g or LimHiFmt_g having more fractional bits than InFmt_g. For Round_g="Trunc_s" no saturation is required.

For static limiting (i.e. UseFixedLimits_g=true), neither rounding nor saturation are required. The internal format is equal to InFmt_g in this case for obvious reasons.

As described in above paragraphs, in most cases no rounding and saturation is required. If they are not required (and disabled by generics) the corresponding registers can be omitted as well.

Example Dynamic Limit¶

Below code shows an example of dynamic limiting, i.e. limits that change at runtime.

i_limit : entity olo.olo_fix_limit
    generic map (
        InFmt_g          => "(1,8,8)",
        LimLoFmt_g       => "(1,8,8)",
        LimHiFmt_g       => "(1,8,8)",
        ResultFmt_g      => "(1,8,8)"
    )
    port map (
        Clk        => Clk,
        Rst        => Rst,
        In_Valid   => X_Valid,
        In_Data    => X_Data,
        In_LimLo   => X_LimLo, -- e.g. from register bank
        In_LimHi   => X_LimHi, -- e.g. from register bank
        Out_Valid  => Y_Valid,
        Out_Result => Y_Data
    );

Example Static Limit¶

Below code shows an example of static limiting, i.e. limits that change at compile-time.

i_limit : entity olo.olo_fix_limit
    generic map (
        InFmt_g          => "(1,8,8)",
        ResultFmt_g      => "(1,8,8)",
        UseFixedLimits_g => true,
        FixedLimLo_g     => -100.75,
        FixedLimHi_g     => 200.125
    )
    port map (
        Clk        => Clk,
        Rst        => Rst,
        In_Valid   => X_Valid,
        In_Data    => X_Data,
        Out_Valid  => Y_Valid,
        Out_Result => Y_Data
    );