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olo_intf_uart

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Status Information

VHDL Source: olo_intf_uart

Description

Overview

This entity implements an UART. It is designed to run high baud-rates (up to 10% of the clock frequency).

Parity checking for RX and parity calculation for TX is done internally in olo_intf_uart.

The Uart_Rx line is synchronized internally inside olo_intf_uart.

The UART protocol is commonly known and hence not described here. A good and concise description of the protocol can be found here.

Generics

Name Type Default Description
ClkFreq_g real - Clock Frequency in Hz
BaudRate_g real 115.2e3 Baud rate
DataBits_g positive 8 Number of data bits
Range: 7 ... 9
StopBits_g string "1" Number of stop bits. Allowed values: "1", "1.5", "2"
Parity_g string "none" Parity setting:
"none" : No parity bit
"even" : parity bit = 0 when there is an even number of ones in data
"odd" : parity but = 0 when there is an odd number of ones in data

Interfaces

Control

Name In/Out Length Default Description
Clk in 1 - Clock - Frequency must e at least 10x higher than BaudRate_g
Rst in 1 - Reset input (high-active, synchronous to Clk)

RX Data Interface

Interface for data received over UART. There is no Ready signal - hence the consumer must be able to accept data immediately.

Name In/Out Length Default Description
Rx_Valid out 1 N/A AXI-S handshaking signal for Rx_Data
Rx_Data out DataBits_g N/A Data received over UART
Rx_ParityError out 1 N/A Asserted if the parity bit does not match the expected value according to the data received (hence there was a bit error).

TX Data Interface

Interface for data to be sent over UART.

Name In/Out Length Default Description
Tx_Valid in 1 '0' AXI-S handshaking signal for Tx_Data
Tx_Ready out 1 N/A AXI-S handshaking signal for Tx_Data
Tx_Data in DataBits_g 0 Data to be sent over UART

UART Interface

Name In/Out Length Default Description
Uart_Tx out 1 N/A UART transmit signal
Uart_Rx in 1 '1' UART receive signal

Detailed Description

No detailed description is given. The UART is very simple.