olo_fix_mix_r2c¶
Status Information¶
VHDL Source: olo_fix_mix_r2c
Bit-true Model: olo_fix_mix_r2c
Description¶
This entity implements a real-to-complex mixer. It multiplies a real input signal (In_SigReal) with a complex local oscillator (In_MixI, In_MixQ) to produce a complex output signal (Out_I, Out_Q).
The downconversion convention is used, which corresponds to multiplying by the conjugate of the local oscillator:
Out_I = +In_SigReal × In_MixI
Out_Q = −In_SigReal × In_MixQ
I (in-phase) and Q (quadrature-phase) components of the local oscillator are presented in parallel. No TDM handling is supported.
The implementation uses two multipliers running in parallel — one for Out_I and one for Out_Q — giving a 2-multiplier architecture.
Latency The latency of this entity is MultRegs_g + 4 clock cycles. Rounding and saturation registers are always enabled.
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| InFmt_g | string | - | Input signal format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| MixFmt_g | string | - | Local oscillator format (for both In_MixI and In_MixQ) String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| OutFmt_g | string | - | Output format (for both Out_I and Out_Q) String representation of an en_cl_fix Format_t (e.g. "(0,1,15)") |
| Round_g | string | "Trunc_s" | Rounding mode String representation of an en_cl_fix FixRound_t. |
| Saturate_g | string | "Warn_s" | Saturation mode String representation of an en_cl_fix FixSaturate_t. |
| MultRegs_g | natural | 1 | Number of pipeline stages for the multiplication |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for all inputs |
| In_SigReal | in | width(InFmt_g) | - | Real input signal Format: InFmt_g |
| In_MixI | in | width(MixFmt_g) | - | Local oscillator in-phase component Format: MixFmt_g |
| In_MixQ | in | width(MixFmt_g) | - | Local oscillator quadrature component Format: MixFmt_g |
In_Valid is the single handshaking signal for all three inputs, which must be presented in parallel. Ready is not supported; the entity accepts data every cycle In_Valid is asserted.
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Valid | out | 1 | - | AXI4-Stream handshaking signal for Out_I and Out_Q |
| Out_I | out | width(OutFmt_g) | - | Result in-phase component Format: OutFmt_g |
| Out_Q | out | width(OutFmt_g) | - | Result quadrature component Format: OutFmt_g |
Detail¶
Architecture¶
The entity uses two independent multipliers operating in parallel:
Out_I = +In_SigReal × In_MixI
Out_Q = −In_SigReal × In_MixQ
The negation of the Q channel is achieved by computing the full-precision product In_SigReal × In_MixQ and then subtracting it from zero before the rounding and saturation stage. This matches the MIX mode behaviour of olo_fix_cplx_mult when the imaginary part of input A is zero, and ensures the Python bit-true model and VHDL produce identical results.
Rounding and saturation are always registered (one clock cycle each), regardless of the Round_g and Saturate_g settings.
