olo_base_sample_hold¶
Status Information¶
VHDL Source: olo_base_sample_hold
Description¶
This entity implemets a sample and hold for a bit-vector. The output holds the last sampled value until a new sample is taken.
This can be used for example as a simiple synchronization mechanism for data-streams with different sample rates or to synchronize feedback paths to the sample rate of the input.
Note that for fixed-point design, a corresponding fixed-point entity olo_fix_sample_hold is available.
Feedback Synchronization¶
olo_base_sample_hold can be used to synchronize feedback paths to the sample rate of the input as depicted in the fiture below.
Below wave depicts that Out_Data might be invalid when new samples arrive (e.g. during In_Data=B). By adding a olo_base_sample_hold in the feedback path, Feedback_Data is ensured to stay valid until the next sample arrives.
An example of using the olo_base_sample_hold for feedback synchronization can be found in the Open Logic Fixed Point Tutorial (see OloFixTutorial).
Data-Stream Synchronization¶
Where data-streams with different sample rates need to be synchronized, olo_base_sample_hold can be used to hold the last value of the faster data-stream until a new sample arrives on the slower data-stream.
The olo_base_sample_hold ensures that the data from ADC-B is held valid until consumed together with data from ADC-A.
Of course this solution only satisfies simple synchronization requirements. Depending on the application, resampling might be required which is not covered by olo_base_sample_hold.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| Width_g | positive | - | Data width |
| ResetValue_g | std_logic_vector | - | Value to apply to output before the first input sample arrives (width must match Width_g) |
| ResetValid_g | boolean | true | True: Out_Valid is asserted after reset (while ResetValue_g is applied) False: Out_Valid is not asserted until the first sample arrives |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_Data | in | Width_g | - | Input data |
| In_Valid | in | 1 | - | AXI4-Stream handshaking signal for In_Data |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Data | out | Width_g | N/A | Output data |
| Out_Valid | out | 1 | N/A | AXI-S handshaking signal for Out_Data |
Detail¶
No detailed description required.