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olo_ft_delay_cfg

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Status Information

VHDL Source: olo_ft_delay_cfg

Description

This component implements an ECC-protected, runtime-configurable delay using SECDED (Single Error Correction, Double Error Detection) Hamming code. The interface and behavior match olo_base_delay_cfg: the input data is delayed by a number of data-beats (In_Valid = '1' cycles) selected through the Delay input. Delay changes settle at the output within less than 5 samples.

The ECC is transparent to the user: data is automatically encoded at the input and decoded/corrected at the output. Error status flags indicate whether a single-bit error was corrected or a double-bit error was detected. In addition to the base entity, RstState_g suppresses reading storage that was never written since reset, so no spurious error flags pollute SEC/DED counters during warm-up.

Generics

Name Type Default Description
Width_g positive - Number of data bits. The internal delay line is wider to accommodate ECC parity bits.
MaxDelay_g positive 256 Maximum delay in data-beats
SupportZero_g boolean false true: Delay = 0 (combinational feed-through) is supported. false: Delay must be >= 1.
RstState_g boolean true true: while the configured delay reaches back to storage never written since reset, the output data and error flags read as zero (covers reset and delay increases beyond the written history). false: such output beats are undefined, including the error flags (base-entity behavior).
RamBehavior_g string "RBW" Controls the RAM behavior. "RBW" or "WBR"
RamStyle_g string "auto" Controls the RAM implementation resource
EccPipeline_g natural 0 0: combinational ECC decode at the output. 1: one In_Valid-gated register on the decoded outputs; the wrapped delay runs one beat shorter (dynamically compensated), so the total delay stays exactly Delay.

Interfaces

Clock and Reset

Name In/Out Length Default Description
Clk in 1 - Clock
Rst in 1 - Reset (high-active, synchronous to Clk). Restarts the RstState_g warm-up gate and clears the internal error-injection latch. The delay-line storage content is unaffected but masked by the warm-up gate.

Control

Name In/Out Length Default Description
Delay in ceil(log2(MaxDelay_g+1)) - Delay in data-beats. Range 1 ... MaxDelay_g (0 allowed with SupportZero_g = true). May be changed at any time; the new delay settles at the output within less than 5 samples.

Data

Name In/Out Length Default Description
In_Data in Width_g - Input data
In_Valid in 1 '1' Data-beat strobe. The delay line only advances on In_Valid = '1' cycles; outputs hold their value in between.
Out_Data out Width_g N/A Delayed output data (corrected if a single-bit error was detected)
Out_EccSec out 1 N/A Single error corrected flag. Time-aligned with Out_Data.
Out_EccDed out 1 N/A Double error detected flag. Output data is unreliable. Time-aligned with Out_Data.

Error Injection (optional)

These ports drive the internal olo_ft_ecc_encode instance. Leave them unconnected for normal operation; see Open Logic Fault-Tolerance Principles - Error Injection for the latched-strobe semantics shared across the ft area.

Name In/Out Length Default Description
In_ErrInj_BitFlip in eccCodewordWidth(Width_g) all 0 Codeword-wide flip pattern. Each '1' bit XORs (flips) the corresponding bit of the stored codeword. Popcount 1 = SEC-correctable, popcount 2 = DED-detectable.
In_ErrInj_Valid in 1 '0' Strobe that latches In_ErrInj_BitFlip into the encoder's pending-injection register. The latched pattern is applied to the next In_Valid beat.

Detailed Description

Architecture

The entity is a sandwich of three Open Logic entities:

  1. olo_ft_ecc_encode encodes each In_Valid beat into a SECDED codeword (combinational).
  2. olo_base_delay_cfg delays the codeword (entity configured with a codeword-wide word).
  3. olo_ft_ecc_decode decodes and corrects the delayed codeword and drives Out_EccSec / Out_EccDed time-aligned with Out_Data.

With EccPipeline_g = 1, one additional In_Valid-gated register is placed on the decoded outputs and the wrapped entity receives Delay - 1, so the total delay stays exactly Delay and the outputs are driven from a fabric register. With SupportZero_g = true the Delay = 0 feed-through bypasses this register combinationally.

Every storage tap of the wrapped entity (the internal shift register stages, the RAM content and the output register) holds a full ECC codeword, so a single upset in any storage medium is corrected at decode. See olo_ft_delay - Storage-Medium Independent Protection for the discussion; it applies here unchanged.

Warm-Up Gating (RstState_g)

The base entity has no reset state: after reset it outputs whatever the delay-line storage holds. For the ECC-protected variant this content decodes as garbage codewords, which would assert spurious Out_EccSec / Out_EccDed flags and pollute error counters.

With RstState_g = true (default), the entity counts the In_Valid beats since reset and forces the output data and both error flags to zero while the configured delay reaches back further than that. This covers both the warm-up after reset and delay increases beyond the written history. Output beats within the written history are never gated; increasing the delay within the written history simply replays older (valid) samples, without spurious flags.

ECC Overhead, Error Injection and Status Flags

See the corresponding sections in Open Logic Fault-Tolerance Principles:

Constraints

  • During the settle window after a delay change (less than 5 samples), the output data follows the base-entity behavior (a mix of old-delay and new-delay samples). The samples are decoded stored codewords, so no spurious error flags occur within the written history.
  • With RstState_g = false the output (including the error flags) is undefined whenever the configured delay reaches back to storage never written since reset. Use the default RstState_g = true where clean flags matter (e.g. when counting SEC/DED events).
  • See Open Logic Fault-Tolerance Principles - Constraints That Apply Across the Area for the constraints that apply across the ft area.