olo_fix_pkg_writer¶

Status Information¶

This is a pure Python utility and therefore does not come with VHDL simulation status.

Usage¶

A detailed example for the usage of olo_fix_pkg_writer can be found in the OloFixTutorial. Below is a brief example for the usage of olo_fix_pkg_writer.

The package is used as shown below:

someFormat = FixFormat(1, 8, 23)
...
writer = olo_fix_pkg_writer()
writer.add_constant("SomeInt", int, 5)
writer.add_constant("SomeFormat", FixFormat, someFormat) # Constant of FixFormat are not allowed for Verilog
writer.add_constant("SomeFormatStr", FixFormat, someFormat, as_string=True)
writer.add_vector("SomeIntVector", int, [1, 2, 3])
# Write VHDL package
writer.write_vhdl_pkg("my_pkg", out_dir)
# Write Verilog header
writer.write_verilog_header("my_hdr", out_dir)

This will generate a VHDL package with the following content:

package my_pkg is
    constant SomeInt : integer := 5;
    constant SomeFormat : FixFormat_t := (1, 8, 23);
    constant SomeFormatStr : string := "(1, 8, 23)";
    constant SomeIntVector : IntegerArray_t := (1, 2, 3);
end package;

And a Verilog header file with the following content:

package my_hdr;
    localparam int SomeInt = 5;
    localparam string SomeFormatStr = "(1, 8, 23)";
    localparam int SomeIntVector [0:2] = '{1, 2, 3};
endpackage : my_hdr

Method Descriptions¶

Generally the methods are documenged in python docstring format.

add_constant¶

def add_constant(self, name: str, type: type, value, as_string=False):

Add a constant to the package.

name: Name of the constant
type: Type of the constant
- Valid options are: int, FixFormat, str, float
value: Value of the constant
as_string: Whether to write the constant as string
- olo_fix entities take number formats as string for verilog compatibility
- For formats that are passed to olo_fix entities, it is recommended to use as_string=True to avoid needless conversion to string in the HDL Code

Note that in Verilog, no FixedFormat type exists. So typle=FixFormat is only allowed in combination with as_string=True for Verilog. In VHDL, both options are allowed and can be used as needed.

add_vector¶

def add_vector(self, name: str, type: type, values: list, as_string=False):

Same as add_constant but for vectors (1D arrays).

write_vhdl_pkg¶

def write_vhdl_pkg(self, pkg_name: str, out_dir: str, olo_library: str = "olo"):

Write VHDL package.

pkg_name: Name of the package
- The file-name is <pkg_name>.vhd
out_dir: Directory to write the package to
olo_library: Library Open Logic is compiled into
- By default Open Logic is compoled to the VHDL library olo
- Only change this setting if you manually changed the library Open Logic is compiled into

write_verilog_header¶

def write_verilog_header(self, pkg_name: str, out_dir: str):

Write Verilog header file.

pkg_name: Name of the header file
- The file-name is <pkg_name>.vh
out_dir: Directory to write the header file to