olo_fix_coef_storage¶
Status Information¶
VHDL Source: olo_fix_coef_storage
Description¶
This entity implements a fixed-point coefficient storage. The storage can be configured as a read-only ROM or as a read-write RAM, allowing coefficients to be updated at runtime.
The intended use case for this entity is to hold coefficients for DSP datapaths. In this context, the entity has the following advantages over using RAMs from olo_base directly:
- Initialization with real values in Init_g, which are quantized to the specified fixed-point format.
- This allows copy-pasting coefficients from tools like Python or MATLAB without needing to pre-quantize them.
- BROM/RAM options for coefficient storage do not need to be implemented separately in the datapath.
- This prevents significant code duplication (many DSP elements require RAM or ROM coefficient storage)
Two independent read ports are provided:
- Coef port - read-only, intended for DSP datapaths that consume coefficients every cycle.
- Cfg port - write port (RAM only) plus optional read-back, intended for software-controlled coefficient updates.
Both ports support a configurable read latency (RdLatency_g).
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| Depth_g | positive | - | Number of coefficient entries |
| Fmt_g | string | - | Coefficient format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| Init_g | string | "0.0" | Comma-separated initial real values (e.g. "1.0, 0.5") Missing entries default to 0.0 |
| StorageType_g | string | "ROM" | "ROM": read-only storage initialized from Init_g "RAM": read-write storage, updateable via the Cfg port |
| RamReadback_g | boolean | false | True: Readback through Cfg_RdData / Cfg_RdValid is possible (RAM only) False: Readback is not possible |
| RamBehavior_g | string | "RBW" | "RBW" = read-before-write, "WBR" = write-before-read For details refer to the description in olo_base_ram_sdp. |
| RdLatency_g | positive | 1 | Read latency in clock cycles for both read ports (minimum 1) |
| MemStyle_g | string | "auto" | Through this generic, the exact resource to use for implementation can be controlled. This generic is applied to the attributes ram_style and ramstyle which vendors offer to control RAM implementation. For details refer to the description or RamStyle_g in olo_base_ram_sdp. Does apply to StorageType_g=ROM as well and can be used to control ROM implementation. |
Note: RamReadback_g=True implements a true-dual-port RAM. Consider technology restrictions and set RamBehavior_g as needed for true dual port RAMs in your target technology.
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Cfg Port¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Cfg_Addr | in | ceil(log2(Depth_g)) | 0 | Address for Cfg read or write |
| Cfg_WrEna | in | 1 | 0 | Write enable - Ignored for StorageType_g=ROM |
| Cfg_WrData | in | width(Fmt_g) | 0 | Data to write - Ignored for StorageType_g=ROM Format: Fmt_g |
| Cfg_RdEna | in | 1 | 0 | Read enable for Cfg readback - Unused for StorageType_g=ROM or RamReadback_g=false |
| Cfg_RdData | out | width(Fmt_g) | N/A | Readback data - Unused for StorageType_g=ROM or RamReadback_g=false Format: Fmt_g |
| Cfg_RdValid | out | 1 | N/A | Read valid for Cfg_RdData - Unused for StorageType_g=ROM or RamReadback_g=false |
Coef Port¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Coef_Addr | in | ceil(log2(Depth_g)) | 0 | Read address |
| Coef_RdEna | in | 1 | 0 | Read enable |
| Coef_RdData | out | width(Fmt_g) | N/A | Coefficient read data Format: Fmt_g |
| Coef_RdValid | out | 1 | N/A | Read valid for Coef_RdData |
Detail¶
Initialization¶
All entries are initialized from Init_g at elaboration time. Init_g is a comma-separated string of real values (e.g. "1.0, 0.5e-1"). Each value is quantized to Fmt_g. Entries with no corresponding Init_g value default to 0.0.
For ROM storage, these initial values are permanent. For RAM storage, they represent the power-on state before any Cfg writes.
Note: Not all FPGA devices do allow initialization of RAMs. Check the documentation of your target device and synthesis tool for details and consider using StorageType_g=ROM if your device does not. SRAM FPGAs typically support RAM initialization.
Read Latency¶
Both the Coef and Cfg read ports have a latency of RdLatency_g clock cycles from the rising edge that samples the address and read-enable to the rising edge where the output is valid. Cfg_RdValid and Coef_RdValid track the latency pipeline and are asserted exactly RdLatency_g cycles after the corresponding RdEna was sampled.
ROM vs RAM¶
When StorageType_g = "ROM", Cfg_WrEna is ignored and the stored values cannot change after elaboration. Cfg_RdData and Cfg_RdValid are always driven to zero.
When StorageType_g = "RAM", coefficients can be updated at runtime via the Cfg write port. Setting RamReadback_g = true additionally enables the Cfg read port so written values can be verified.
Read-Before-Write vs Write-Before-Read¶
When StorageType_g = "RAM" and a Cfg write and a Coef read target the same address in the same clock cycle, RamBehavior_g determines which value the Coef port returns:
- "RBW": the Coef port returns the value that existed before the write.
- "WBR": the Coef port returns the value after the write has been applied.