olo_base_rate_limit¶
Status Information¶
VHDL Source: olo_base_rate_limit
Description¶
This component limits the rate of AXI4-Stream style handshaked interfaces to a specified maximum data rate. It can be used to avoid overloading downstream components. This is especially useful when interfacing to components that have limited processing capabilities and do not support back-pressure (i.e. do not de-assert Ready signals). Another common use-case is limiting the bandwidth of data-streams - thanks to runtime configurable parameters the rate limit can be adjusted on-the-fly.
The component has two modes of operation:
- BLOCK: In this mode the component does not forward more than a limited number of samples over a given period but still does forward short bursts at full speed as long as the average rate is not exceeded.
- SMOOTH: In this mode the component spaces samples evenly over time to achieve a constant output data rate.
BLOCK Mode¶
The sample figure is drawn for Period_g=4 clock cycles and MaxSamples_g=2 samples per period. Periods on the output side are marked in colors.
Note how the rate can exceed the limit if short bursts occur at the end of one block (blue, block 2) and the beginning of the next block (turquoise, block 3). Although each block only forwards two samples, in this situation fours samples are forwarded consecutively in the two consecutive blocks.
SMOOTH Mode¶
The sample figure is drawn for Period_g=4 clock cycles and MaxSamples_g=2 samples per period. Periods on the output side are marked in colors.
Note how the samples are equally spaced (one sample every two clock cycles). In contrast to BLOCK mode bursts are forwarded.
Runtime Configuration¶
When RuntimeCfg_g=false (default), the component operates with fixed parameters defined by the Period_g and MaxSamples_g generics.
When RuntimeCfg_g=true, the component accepts runtime configuration through the Cfg_Period and Cfg_MaxSamples ports. In this mode:
- The generics Period_g and MaxSamples_g define the maximum supported values
- The actual period and max samples are determined by the configuration ports
- Configuration port values represent the actual value minus 1 (e.g., Cfg_Period=1 means a period of 2 clock cycles)
- Configuration changes take effect within less than five clock cycles
- The configuration ports must always satisfy: Cfg_MaxSamples ≤ Cfg_Period
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| Width_g | positive | - | Width of In_Data and Out_Data |
| RegisterReady_g | boolean | true | If true, In_Ready is registered to improve timing |
| Mode_g | string | "SMOOTH" | Rate limiting mode, either "BLOCK" or "SMOOTH" |
| Period_g | positive | - | Time period for rate limiting in clock cycles. When RuntimeCfg_g=true, this defines the maximum supported period. |
| MaxSamples_g | positive | 1 | Maximum number of samples allowed per Period_g. When RuntimeCfg_g=true, this defines the maximum supported samples per period. |
| RuntimeCfg_g | boolean | false | If true, period and max samples are taken from configuration ports instead of generics |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Configuration¶
Configuration ports are only used when RuntimeCfg_g=true.
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Cfg_Period | in | ceil(log2(Period_g)) | Period_g-1 | Period for runtime-configuration minus 1 (Cfg_Period=1 means a period of two clock cycles) |
| Cfg_MaxSamples | in | ceil(log2(MaxSamples_g)) | MaxSamples_g-1 | MaxSamples for runtime-configuration minus 1 (Cfg_MaxSamples=1 means two samples per block) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| In_Data | in | Width_g | - | Input data |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for In_Data |
| In_Ready | out | 1 | N/A | AXI4-Stream handshaking signal for In_Data |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_Data | out | Width_g | N/A | Output data |
| Out_Valid | out | 1 | N/A | AXI4-Stream handshaking signal for Out_Data |
| Out_Ready | in | 1 | '1' | AXI4-Stream handshaking signal for Out_Data |
Architecture¶
The architecture is trivial and therefore not documented in detail.
For RegisterReady_g=true, a olo_base_pl_stage is used to register the data-stream on the input side (before the rate limiting logic).