olo_fix_cplx_addsub¶
Status Information¶
VHDL Source: olo_fix_cplx_addsub
Bit-true Model: olo_fix_cplx_addsub
Description¶
This entity performs addition or subtraction of two complex fixed-point numbers. (I in-phase) and Q (quadrature-phase) can be handled parallel or TDM on inputs and outputs.
Latency of this entity is OpRegs_g clock cycles plus optional rounding and saturation registers. The default generics lead to a latency of 3 clock cycles.
For details about the fixed-point number format used in Open Logic, refer to the fixed point principles.
Generics¶
| Name | Type | Default | Description |
|---|---|---|---|
| AFmt_g | string | - | Input A format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| BFmt_g | string | - | Input B format String representation of an en_cl_fix Format_t (e.g. "(1,1,15)") |
| ResultFmt_g | string | - | Format of the result String representation of an en_cl_fix Format_t (e.g. "(0,1,15)") |
| Operation_g | string | "Add" | Operation to perform "Add": Perform addition "Sub": Perform subtraction |
| Round_g | string | "Trunc_s" | Rounding mode String representation of an en_cl_fix FixRound_t. |
| Saturate_g | string | "Warn_s" | Saturation mode String representation of an en_cl_fix FixSaturate_t. |
| OpRegs_g | natural | 1 | Number of pipeline stages for the operation |
| RoundReg_g | string | "YES" | Presence of rounding pipeline stage "YES": Always implement register "NO": Never implement register "AUTO": Implement register if rounding is needed according to the formats chosen |
| SatReg_g | string | "YES" | Presence of saturation pipeline stage "YES": Always implement register "NO": Never implement register "AUTO": Implement register if saturation is needed according to the formats chosen |
| IqHandling_g | string | "Parallel" | "Parallel" - I/Q arrive in parallel, ports InA_I and InA_Q are used "TDM" - I/Q arrive TDM, port InA_IQ is used |
Interfaces¶
Control¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Clk | in | 1 | - | Clock |
| Rst | in | 1 | - | Reset input (high-active, synchronous to Clk) |
Input Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| InA_I | in | width(AFmt_g) | - | Input data in-phase for IqHandling_g=Parallel Format: AFmt_g |
| InA_Q | in | width(AFmt_g) | - | Input data quadrature-phase for IqHandling_g=Parallel Format: AFmt_g |
| InA_IQ | in | width(AFmt_g) | - | Input data for IqHandling_g=TDM Format: AFmt_g |
| InB_I | in | width(BFmt_g) | - | Input data in-phase for IqHandling_g=Parallel Format: BFmt_g |
| InB_Q | in | width(BFmt_g) | - | Input data quadrature-phase for IqHandling_g=Parallel Format: BFmt_g |
| InB_IQ | in | width(BFmt_g) | - | Input data for IqHandling_g=TDM Format: BFmt_g |
| In_Valid | in | 1 | '1' | AXI4-Stream handshaking signal for InA and InB |
| In_Last | in | 1 | '0' | Used for optional TDM synchronization for IqHandling=TDM. |
Output Data¶
| Name | In/Out | Length | Default | Description |
|---|---|---|---|---|
| Out_I | out | width(ResultFmt_g) | N/A | Result data in-phase for IqHandling_g=Parallel Format ResultFmt_g |
| Out_Q | out | width(ResultFmt_g) | N/A | Result data quadrature-phase for IqHandling_g=Parallel Format ResultFmt_g |
| Out_IQ | out | width(ResultFmt_g) | N/A | Result data for IqHandling_g=TDM Format ResultFmt_g |
| Out_Valid | out | 1 | N/A | AXI4-Stream handshaking signal for Out_I, Out_Q, Out_IQ |
| Out_Last | out | 1 | N/A | Used for optional TDM synchronization for IqHandling=TDM. |
Detail¶
No detail description required.