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olo_ft_cc_pulse

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Status Information

VHDL Source: olo_ft_cc_pulse

Description

This component is a TMR-hardened pulse clock domain crossing. A single-event upset (SEU) on any flip-flop of the crossing is masked: it neither creates nor removes an output pulse.

It is the fault-tolerant counterpart of olo_base_cc_pulse with the same interface and the same behavior: every single-cycle pulse on In_Pulse produces exactly one single-cycle pulse on Out_Pulse. The entity works for any clock ratio.

The pulse frequency must be significantly lower than the slower clock frequency. Two pulses on the same bit must be at least 3 + SyncStages_g cycles of the slower clock apart. Pulses that follow each other more closely may be merged into one output pulse.

This block follows the general clock-crossing principles. Read through them for more information.

Generics

Name Type Default Description
NumPulses_g positive 1 Number of independent pulse channels
SyncStages_g positive 2 Number of synchronization stages.
Range: 2 ... 4

Interfaces

Name In/Out Length Default Description
In_Clk in 1 - Source clock
In_RstIn in 1 '0' Reset input (high-active, synchronous to In_Clk)
In_RstOut out 1 N/A Reset output (see clock-crossing principles, synchronous to In_Clk)
In_Pulse in NumPulses_g - Input pulses (synchronous to In_Clk)
Out_Clk in 1 - Destination clock
Out_RstIn in 1 '0' Reset input (high-active, synchronous to Out_Clk)
Out_RstOut out 1 N/A Reset output (see clock-crossing principles, synchronous to Out_Clk)
Out_Pulse out NumPulses_g N/A Output pulses (synchronous to Out_Clk), one single-cycle pulse per input pulse

Architecture

The architecture follows olo_base_cc_pulse: every input pulse toggles a level, the level crosses the clock domain and an edge detector converts every change of the level back into a single-cycle pulse. Each pulse channel is one olo_ft_private_cc_toggle; the resets of both domains are crossed once by olo_ft_cc_reset.

           In_Clk domain               :                Out_Clk domain
                                       :
In_Pulse --> XOR --> ToggleIn --> olo_ft_cc_bits --> ToggleOut --+-------------> XOR --> Out_Pulse
              ^         |              :          (3 chains +    |               ^
              |         v              :           voter)        v               |
            vote <- ToggleLast[A,B,C]  :                 ToggleOutLast[A,B,C] -> vote
  • Toggle register (In_Clk): three copies. The next value of every copy is computed from the voted value, so an upset copy is repaired at the next clock edge.
  • Synchronizer: olo_ft_cc_bits with three independent synchronizer chains and a majority voter. Because a toggle is a level, the three chains may see a toggle one clock cycle apart, but the voted level still changes exactly once per input pulse.
  • Edge detector (Out_Clk): three copies of the last level with a voter.

The design contains no latches. Every path between the clock domains starts and ends at a flip-flop and is constrained like the paths of olo_ft_cc_bits.

Limitations

  • TMR masks one upset per register and clock cycle. Two upsets in different copies of the same register within one clock cycle are not masked.
  • The voters and the combinational logic are not triplicated. The design targets upsets of storage elements (SEU), not single-event transients in combinational logic.
  • The reset crossing olo_ft_cc_reset protects its acknowledge paths with TMR. An upset in its request-path registers leads to a spurious reset of both clock domains, not to a spurious output pulse.

History

Earlier versions implemented the short-pulse synchronizer of Li, Nelson and Wirthlin [1] (Fig. 14) with a set/reset latch per TMR copy. FPGA tools map such a latch to a transparent latch whose gate and data input both follow the input pulse, so the end of the pulse races the closing of the latch (a pulse can be lost), and the paths through the latch are not timed. The toggle-based architecture avoids latches and supports any clock ratio.

Constraints

The same constraints as for olo_base_cc_pulse apply, see clock-crossing principles.

Note that the scoped constraints for automatic constraining in AMD Vivado are only provided for the olo_base clock crossings. Constrain the clock crossings of olo_ft entities manually.

References

[1] Y. Li, B. Nelson, and M. Wirthlin, "Synchronization Techniques for Crossing Multiple Clock Domains in FPGA-Based TMR Circuits," IEEE Transactions on Nuclear Science, vol. 57, no. 6, pp. 3506-3514, Dec. 2010. DOI: 10.1109/TNS.2010.2086075