Skip to content

olo_ft_cc_reset

Back to Entity List

Status Information

VHDL Source: olo_ft_cc_reset

Description

TMR-hardened clock crossing for resets, the fault-tolerant counterpart to olo_base_cc_reset with the same interface and behavior.

Reset on either side is asserted on the other clock domain immediately and de-asserted synchronously to the corresponding clock. The reset is clock-crossed in both directions.

Generics

Name Type Default Description
SyncStages_g positive 2 Number of sync stages per TMR chain in the internal olo_ft_cc_bits (range 2-4).

Interfaces

Name In/Out Length Default Description
A_Clk in 1 - Clock of domain A
A_RstIn in 1 '0' Reset input in domain A (active high)
A_RstOut out 1 N/A Synchronized reset output in domain A
B_Clk in 1 - Clock of domain B
B_RstIn in 1 '0' Reset input in domain B (active high)
B_RstOut out 1 N/A Synchronized reset output in domain B

Detailed Description

The component behaves identically to olo_base_cc_reset. See that component's documentation for the full protocol description. The entity is structurally identical to olo_base_cc_reset; the only difference is that each of the two internal acknowledge-path synchronizers is a TMR-hardened olo_ft_cc_bits instead of the non-TMR olo_base_cc_bits. This protects the ack paths against single-event upsets in radiation environments.

Note that the local request-path registers (RstALatch, RstBLatch, RstRqstB2A, RstRqstA2B) are not manually triplicated in this entity. They should be covered by vendor TMR (syn_radhardlevel = "tmr") as part of the surrounding radiation-hardened design.

Relationship to Other Components

References

[1] Y. Li, B. Nelson, and M. Wirthlin, "Synchronization Techniques for Crossing Multiple Clock Domains in FPGA-Based TMR Circuits," IEEE Transactions on Nuclear Science, vol. 57, no. 6, pp. 3506-3514, Dec. 2010. DOI: 10.1109/TNS.2010.2086075